Patents by Inventor Philip Clarke
Philip Clarke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141053Abstract: The disclosure provides TNF-like ligand 1a (TL1a)-binding proteins comprising an antigen binding domain of an antibody which binds specifically to TL1a and inhibits interaction of TL1a and Death Receptor 3 (DR3) and which does not inhibit the interaction of TL1a and Decoy Receptor 3 (DcR3). The disclosure also provides uses of the TL1a-binding proteins.Type: ApplicationFiled: April 20, 2023Publication date: May 2, 2024Inventors: Lynn Dorothy POULTON, Adam CLARKE, Andrew James POW, Debra TAMVAKIS, George KOPSIDAS, Anthony Gerard DOYLE, Philip Anthony JENNINGS, Matthew POLLARD
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Patent number: 11248016Abstract: The invention may provide, in part, compounds for use as antiproliferative, chemotherapeutic, antiviral, cell sensitising or adjuvant agents, and pharmaceutical compositions including the compounds. The compounds may be for use in treating diseases and disorders related to cell proliferation such as cancer, or in treating diseases and disorder which are linked to aberrant control of protein synthesis, such as cancer, viral infection, muscle wasting, autistic spectrum disorders, Alzheimer's disease, Huntingdon's disease and Parkinson's disease.Type: GrantFiled: July 25, 2019Date of Patent: February 15, 2022Assignee: THE UNIVERSITY OF NOTTINGHAMInventors: Andrew Bottley, Christopher Hayes, Graham Seymour, Anna Grabowska, Philip Clarke
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Publication number: 20190382433Abstract: The invention may provide, in part, compounds for use as antiproliferative, chemotherapeutic, antiviral, cell sensitising or adjuvant agents, and pharmaceutical compositions including the compounds. The compounds may be for use in treating diseases and disorders related to cell proliferation such as cancer, or in treating diseases and disorder which are linked to aberrant control of protein synthesis, such as cancer, viral infection, muscle wasting, autistic spectrum disorders, Alzheimer's disease, Huntingdon's disease and Parkinson's disease.Type: ApplicationFiled: July 25, 2019Publication date: December 19, 2019Applicant: THE UNIVERSITY OF NOTTINGHAMInventors: ANDREW BOTTLEY, CHRISTOPHER HAYES, GRAHAM SEYMOUR, ANNA GRABOWSKA, PHILIP CLARKE
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Patent number: 10428102Abstract: The invention may provide, in part, compounds for use as antiproliferative, chemotherapeutic, antiviral, cell sensitizing or adjuvant agents, and pharmaceutical compositions including the compounds. The compounds may be for use in treating diseases and disorders related to cell proliferation such as cancer, or in treating diseases and disorders which are linked to aberrant control of protein synthesis, such as cancer, viral infection, muscle wasting, autistic spectrum disorders, Alzheimer's disease, Huntingdon's disease and Parkinson's disease.Type: GrantFiled: April 7, 2015Date of Patent: October 1, 2019Assignee: THE UNIVERSITY OF NOTTINGHAMInventors: Andrew Bottley, Christopher Hayes, Graham Seymour, Anna Grabowska, Philip Clarke
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Publication number: 20170275323Abstract: A compound of Formula I: R1-L1-C(A)(A?)-CH2, -L2-R2 or a pharmaceutically acceptable salt thereof, for use in medicine, for example in the treatment of a disease or condition selected from the group comprising cancer, autistic spectrum disorders.Type: ApplicationFiled: April 7, 2015Publication date: September 28, 2017Applicant: THE UNIVERSITY OF NOTTINGHAMInventors: ANDREW BOTTLEY, CHRISTOPHER HAYES, GRAHAM SEYMOUR, ANNA GRABOWSKA, PHILIP CLARKE
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Patent number: 9477586Abstract: Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.Type: GrantFiled: November 3, 2011Date of Patent: October 25, 2016Assignee: Altera CorporationInventors: Sam Hedinger, Philip Clarke
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Publication number: 20130160905Abstract: A method for producing a tempered martensitic heat resistant steel for high temperature applications at an application temperature of up to 650° C. and to a steel produced by the method. The use of the steel in the production of components for high temperature applications such as turbine blades or casings, bolting and boiler tubes, heat exchangers or other elements in power generation systems.Type: ApplicationFiled: June 10, 2011Publication date: June 27, 2013Applicant: TATA STEEL NEDERLAND TECHNOLOGY BVInventors: Urszula Alicja Sachadel, Peter Francis Morris, Philip Clarke, Cheng Liu
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Publication number: 20120281493Abstract: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Inventor: Philip Clarke
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Patent number: 8223584Abstract: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.Type: GrantFiled: April 29, 2009Date of Patent: July 17, 2012Assignee: Altera CorporationInventor: Philip Clarke
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Patent number: 7990786Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.Type: GrantFiled: August 11, 2009Date of Patent: August 2, 2011Assignee: Altera CorporationInventors: Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke, Manoj B. Roge
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Patent number: 7990783Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.Type: GrantFiled: January 11, 2011Date of Patent: August 2, 2011Assignee: Altera CorporationInventors: Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu
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Patent number: 7983094Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.Type: GrantFiled: August 11, 2009Date of Patent: July 19, 2011Assignee: Altera CorporationInventors: Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Yan Chong
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Patent number: 7928770Abstract: I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.Type: GrantFiled: November 5, 2007Date of Patent: April 19, 2011Assignee: Altera CorporationInventors: Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong, Michael H. M. Chu, Manoj B. Roge
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Patent number: 7898296Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.Type: GrantFiled: November 23, 2009Date of Patent: March 1, 2011Assignee: Altera CorporationInventors: Ning Xue, Philip Clarke, Joseph Huang, Yan Chong
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Patent number: 7876630Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.Type: GrantFiled: November 6, 2007Date of Patent: January 25, 2011Assignee: Altera CorporationInventors: Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu
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Patent number: 7791375Abstract: Read interface circuitry is disclosed that facilitates using a source-synchronous clock signal to calibrate the read interface. In one embodiment, configurable read interface circuitry allows a particular read path to be configured for use in calibrating a read interface of the destination device. In particular, a plurality of read paths are provided, each read path having a configurable multiplexor (“mux”) coupled to a capture register of the read path such that the mux can be configured to select either an input coupled to an inverted output of the capture register or an input coupled to a prior register in the read data path. When the inverted output of the capture register is selected, a source-synchronous clock signal (e.g., DQS or delayed DQS signal) provided at the capture register's clock input results in a toggle signal at the capture register's output. In one embodiment, that toggle signal is provided to a re-sync register clocked by a re-sync clock signal.Type: GrantFiled: July 10, 2009Date of Patent: September 7, 2010Assignee: Altera CorporationInventor: Philip Clarke
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Patent number: 7688116Abstract: Circuitry and methods are disclosed for capturing data from a double-data rate signal received from a source circuit, converting the double-data rate signal to single and/or half rate data signals, and re-synchronizing the data to the destination circuit's clock signal. In one embodiment, a first set of registers converts a double-data rate signal synchronized to a full-rate clock signal to two single-data rate signals. A second set of registers converts the single-data rate signals to four half-data rate signals. A third set of registers synchronizes the half-rate data signals to a half-rate clock signal.Type: GrantFiled: May 9, 2008Date of Patent: March 30, 2010Assignee: Altera CorporationInventors: Philip Wise, Philip Clarke
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Patent number: 7642812Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.Type: GrantFiled: August 24, 2007Date of Patent: January 5, 2010Assignee: Altera CorporationInventors: Ning Xue, Philip Clarke, Joseph Huang, Yan Chong
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Publication number: 20090296503Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Applicant: Altera CorporationInventors: Michael H.M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke, Manoj B. Roge
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Patent number: 7593273Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.Type: GrantFiled: November 5, 2007Date of Patent: September 22, 2009Assignee: Altera CorporationInventors: Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke, Manoj B. Roge