Abstract: An apparatus for detecting a storm, including a partially transparent housing defining a cavity and a suspended magnetic element positioned within the cavity. The magnetic element is rotatable in a first plane and pivotable in second plane and third planes, wherein the second plane is perpendicular to the first plane and the third plane is perpendicular to the first plane and perpendicular to the second plane. A rapid pivot of the magnetic element away from the pull of gravity signals a close proximity of a storm. A first sensor operationally connected to the magnetic element for measuring the deflection of the magnetic element, dampening fluid substantially fills the cavity, a second sensor positioned within the housing for measuring the degree to which the magnetic element is level, and a laser operationally connected to the magnetic element and positioned to emit a beam of light corresponding to the orientation of the magnetic element.

Abstract: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.

Abstract: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Abstract: I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: Circuits, methods, and apparatus that isolate an input register from spurious transitions on a DQS signal. One example receives an enable signal from a core. A logic circuit, which may be referred to as a one-half period circuit, shortens enable pulses at their front end by one-half a period. The shortened enable signal is passed to a storage element such as a register. Active pulses of the shortened enable signal clear the register, which provides a control signal closing a switch, such as an AND gate. The switch passes the DQS signal to the input register when closed and isolates the input register from the DQS signal when open. The shortened enable signal prevents the switch from opening early and passing spurious transitions on the DQS signal, for example during back-to-back non-consecutive read cycles.

Abstract: Read interface circuitry is disclosed that facilitates using a source-synchronous clock signal to calibrate the read interface. In one embodiment, configurable read interface circuitry allows a particular read path to be configured for use in calibrating a read interface of the destination device. In particular, a plurality of read paths are provided, each read path having a configurable multiplexor (“mux”) coupled to a capture register of the read path such that the mux can be configured to select either an input coupled to an inverted output of the capture register or an input coupled to a prior register in the read data path. When the inverted output of the capture register is selected, a source-synchronous clock signal (e.g., DQS or delayed DQS signal) provided at the capture register's clock input results in a toggle signal at the capture register's output. In one embodiment, that toggle signal is provided to a re-sync register clocked by a re-sync clock signal.

Abstract: Circuitry and methods are disclosed for capturing data from a double-data rate signal received from a source circuit, converting the double-data rate signal to single and/or half rate data signals, and re-synchronizing the data to the destination circuit's clock signal. In one embodiment, a first set of registers converts a double-data rate signal synchronized to a full-rate clock signal to two single-data rate signals. A second set of registers converts the single-data rate signals to four half-data rate signals. A third set of registers synchronizes the half-rate data signals to a half-rate clock signal.

Abstract: Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Abstract: Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

Abstract: The present invention relates to 6,7-dihydro-5H-pyrazolo[1,2a]pyrazol-1-ones which inhibit the extracellular release of inflammatory cytokines, said cytokines responsible for one or more human or higher mammalian disease states. The present invention further relates to compositions comprising said 6,7-dihydro-5H-pyrazolo[1,2a]pyrazol-1-ones and methods for preventing, abating, or otherwise controlling enzymes which are understood to be the active components responsible for the herein described disease states.

Abstract: The present invention relates to 6,7-dihydro-5H-pyrazolo[1,2?]pyrazol-1-ones which inhibit the extracellular release of inflammatory cytokines, said cytokines responsible for one or more human or higher mammalian disease states. The present invention further relates to compositions comprising said 6,7-dihydro-5H-pyrazolo[1,2?]pyrazol-1-ones and methods for preventing, abating, or otherwise controlling enzymes which are understood to be the active components responsible for the herein described disease states.

Abstract: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Abstract: A method for assembling a turbine nozzle for a gas turbine engine facilitates improving cooling efficiency of the turbine nozzle. The method includes providing a hollow doublet including a leading airfoil and a trailing airfoil coupled by at least one platform, wherein each airfoil includes a first sidewall and a second sidewall that extend between a respective leading and trailing edge. The method also includes inserting an insert into at least one of the airfoils, wherein the insert includes a first sidewall including a first plurality of cooling openings that extending therethrough, and a second sidewall including a second plurality of cooling openings extending therethrough, and wherein the first plurality of cooling openings facilitate more cooling of the airfoil than the second plurality of cooling openings.