Patents by Inventor Philip J. Oldiges
Philip J. Oldiges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170054005Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.Type: ApplicationFiled: November 30, 2015Publication date: February 23, 2017Inventors: Chung H. Lam, Chung-Hsun Lin, Darsen D. Lu, Philip J. Oldiges
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Patent number: 9553173Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.Type: GrantFiled: December 8, 2015Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung H. Lam, Chung-hsun Lin, Darsen D. Lu, Philip J. Oldiges
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Patent number: 9515171Abstract: Techniques for producing radiation tolerant device structures are provided. In one aspect, a method for forming a radiation-hardened device includes the steps of: forming fin masks on a SOI layer of an SOI wafer, wherein the SOI wafer includes the SOI layer separated from a substrate by a buried insulator; patterning fins in the SOI layer using the fin masks; and implanting at least one dopant into exposed portions of the buried insulator between the fins to increase a radiation hardness of the device structure by providing a path in the buried insulator for charge to dissipate, wherein the fin masks are left in place during the implanting step to prevent damage to the fins. Implementations with a bulk substrate, as well as the resulting devices, are also provided.Type: GrantFiled: October 22, 2015Date of Patent: December 6, 2016Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Philip J. Oldiges
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Publication number: 20160247888Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.Type: ApplicationFiled: February 19, 2015Publication date: August 25, 2016Inventors: Pranita Kerber, Effendi Leobandung, Philip J. Oldiges
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Patent number: 9064739Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.Type: GrantFiled: September 17, 2013Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Wilfried E. A. Haensch, Chung-Hsun Lin, Philip J. Oldiges, Kern Rim
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Patent number: 9058441Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: June 27, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Patent number: 9034715Abstract: A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.Type: GrantFiled: March 12, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Yanfeng Wang, Dechao Guo, Darsen Lu, Philip J. Oldiges, Gan Wang, Xin Wang
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Patent number: 8993395Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor.Type: GrantFiled: June 21, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus
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Patent number: 8940558Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Wilfried E. A. Haensch, Chung-Hsun Lin, Philip J. Oldiges, Kern Rim
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Publication number: 20150014752Abstract: A thin body field effect transistor (FET) nanopore sensor includes a silicon on insulator (SOI) structure having an annular shape and comprising a source, a drain and a thin body channel interposed therebetween. A nanopore is formed in a central opening of the SOI structure. A gate dielectric is disposed on the SOI structure insulating the SOI structure from a liquid gate within the nanopore. A back gate is formed around the SOI structure. A shallow trench isolation (STI) layer is formed between the SOI structure and the back gate.Type: ApplicationFiled: July 12, 2013Publication date: January 15, 2015Inventors: CHRISTOPHER P. D'EMIC, RAMACHANDRAN MURALIDHAR, PHILIP J. OLDIGES, SUFI ZAFAR
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Patent number: 8921939Abstract: A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.Type: GrantFiled: January 28, 2013Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel C. Ontalus, Kai Xiu
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Patent number: 8890256Abstract: The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.Type: GrantFiled: March 20, 2009Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Mark C. Hakey, Tak H. Ning, Philip J. Oldiges, Henry H. K. Tang
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Publication number: 20140310676Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: June 27, 2014Publication date: October 16, 2014Inventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140273298Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilfried E.A. Haensch, Chung-Hsun Lin, Philip J. Oldiges, Kern Rim
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Publication number: 20140264591Abstract: A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yanfeng Wang, Dechao Guo, Darsen Lu, Philip J. Oldiges, Gan Wang, Xin Wang
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Publication number: 20140266254Abstract: Techniques for quantifying ?Dfin in FINFET technology are provided. In one aspect, a method for quantifying ?Dfin between a pair of long channel FINFET devices includes the steps of: (a) obtaining Vth values for each of the long channel FINFET devices in the pair; (b) determining a ?Vth for the pair of long channel FINFET devices; and (c) using the ?Vth to determine the ?Dfin between the pair of long channel FINFET devices, wherein the ?Vth is a function of a difference in a Qbody and a gate capacitance between the pair of long channel FINFET devices, and wherein the Qbody is a function of Dfin and Nch for each of the long channel FINFET devices in the pair, and as such the ?Vth is proportional to the ?Dfin between the pair of long channel FINFET devices.Type: ApplicationFiled: September 17, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Wilfried E.A. Haensch, Chung-Hsun Lin, Philip J. Oldiges, Kern Rim
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Patent number: 8806419Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: August 20, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Patent number: 8799848Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: January 15, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201700Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: August 20, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201699Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams