Patents by Inventor Philip J. Oldiges
Philip J. Oldiges has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110115022Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Dechao Guo, Pranita Kulkarni, Philip J. Oldiges, Ghavam G. Shahidi
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Publication number: 20110102042Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: January 8, 2011Publication date: May 5, 2011Applicant: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7923782Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.Type: GrantFiled: February 27, 2004Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
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Publication number: 20110037128Abstract: Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.Type: ApplicationFiled: August 15, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya N. Chakravarti, Dechao Guo, Wilfried Ernst-August Haensch, Pranita Kulkarni, Fei Liu, Philip J. Oldiges, Keith Kwong Hon Wong
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Patent number: 7888959Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: GrantFiled: September 19, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Patent number: 7883944Abstract: A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.Type: GrantFiled: March 19, 2009Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Bruce B. Doris, Philip J. Oldiges
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Publication number: 20100237389Abstract: The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device.Type: ApplicationFiled: March 20, 2009Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark C. HAKEY, Tak H. Ning, Philip J. Oldiges, Henry H.K. Tang
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Publication number: 20100237410Abstract: A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.Type: ApplicationFiled: March 19, 2009Publication date: September 23, 2010Applicant: International Business Machines CorporationInventors: HUILONG ZHU, BRUCE B. DORIS, PHILIP J. OLDIGES
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Patent number: 7791169Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: GrantFiled: April 18, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Patent number: 7785944Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.Type: GrantFiled: March 24, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges
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Patent number: 7767503Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.Type: GrantFiled: June 4, 2008Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
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Patent number: 7691482Abstract: The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.Type: GrantFiled: June 23, 2006Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Bruce B. Doris, Meikei Ieong, Philip J. Oldiges, Min Yang
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Patent number: 7627840Abstract: A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.Type: GrantFiled: July 13, 2006Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: A J Kleinosowski, Philip J. Oldiges, Paul M. Solomon, Richard Q. Williams
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Publication number: 20090134925Abstract: A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.Type: ApplicationFiled: September 19, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan H. Cannon, AJ KleinOsowski, K. Paul Muller, Tak H. Ning, Philip J. Oldiges, Leon J. Sigal, James D. Warnock, Dieter Wendel
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Publication number: 20090072313Abstract: A series transistor device includes a series source, a series drain, a first constituent transistor, and a second constituent transistor. The first constituent transistor has a first source and a first drain, and the second constituent transistor has a second source and a second drain. All of the constituent transistors have a same conductivity type. The series source is the first source, and the series drain is the second drain. A drain of one of the constituent transistors is merged with a source of another of the constituent transistors.Type: ApplicationFiled: September 19, 2007Publication date: March 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Wilfried E. Haensch, Tak H. Ning, Philip J. Oldiges, Ghavam G. Shahidi
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Patent number: 7452761Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.Type: GrantFiled: October 11, 2007Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
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Publication number: 20080242069Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.Type: ApplicationFiled: June 4, 2008Publication date: October 2, 2008Inventors: Huilong Zhu, Philip J. Oldiges, Bruce B. Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
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Publication number: 20080191314Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: ApplicationFiled: April 18, 2008Publication date: August 14, 2008Applicant: International Busines Machines CorporationInventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
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Publication number: 20080176365Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.Type: ApplicationFiled: March 24, 2008Publication date: July 24, 2008Inventors: Huilong Zhu, Bruce B. Doris, Xinlin Wang, Jochen Beintner, Ying Zhang, Philip J. Oldiges
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Patent number: 7388274Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.Type: GrantFiled: August 15, 2007Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong