Abstract: A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching the stack, to expose the substrate and keep the stack in the form of a line; forming insulating spacers on the lateral walls of the line; performing an epitaxial growth of a single-crystal semiconductor on the substrate, on either side of the line; selectively removing the third insulating layer to partially expose the second insulating layer at a predetermined location; and depositing and etching a conductive material to fill the cavity formed by the previous removal of the third insulating layer.

Abstract: A process for producing an electronic component includes covering a substrate with a portion defining, with the substrate, a volume at least partly filled with a temporary material. The temporary material is then removed via chimney for access to said volume. A deposition of a fill material is then made in said volume, the fill material being obtained from precursors supplied via the chimney. The process is particularly suitable for producing a gate of an MOS-type transistor. In this case, the fill material is conducting or semiconducting, and an electrically insulating coating material may also be deposited in said volume before the (semi) conducting fill material. The process also includes defining a trench in a substrate filled with a temporary material. The filled trench is then covered with a circuit portion. The temporary material is then removed via a chimney for access to the trench. A deposition of low dielectric fill material is then made in the trench.

Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Abstract: A semiconductor device is provided that includes a semiconductor channel region extending above a semiconductor substrate in a longitudinal direction between a semiconductor source region and a semiconductor drain region, and a gate region extending in the transverse direction, coating the channel region, and insulated from the channel region. The source, channel, and drain regions are formed in a continuous semiconductor layer that is approximately plane and parallel to the upper surface of the substrate. Additionally, the source, drain, and gate regions are coated in an insulating coating so as to provide electrical insulation between the gate region and the source and drain regions, and between the substrate and the source, drain, gate, and channel regions. Also provided is an integrated circuit that includes such a semiconductor device, and a method for manufacturing such a semiconductor device.

Abstract: An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.

Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.

Abstract: A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

Abstract: A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.

Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.

Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.

Abstract: An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.

Abstract: The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract: A method for forming contact openings in various locations of the upper surface of an integrated circuit having raised areas, critical openings having to be formed between two neighboring raised areas, including the steps of covering the entire structure with a first protection layer; forming non-critical openings in the first protection layer; coating the structure with a second protection layer; performing an oblique irradiation so that the second protection layer is not irradiated at the bottom of the regions located between two raised areas; removing the non-irradiated portions of the second protection layer; removing the portions of the first protection layer located under the second protection layer at the locations where this second protection layer has been removed; and removing the irradiated portions of the second protection layer.

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

Abstract: A method for manufacturing buried connections in an integrated circuit, including the steps of: providing a structure formed of a first support wafer glued at the rear surface of a thin semiconductor wafer, one or several elements of the integrated circuit being possibly formed in and above the thin wafer; gluing a second support wafer on the structure on the front surface side of the thin wafer; removing the first support wafer; forming connections between different areas of the rear surface of the thin wafer; gluing a third support wafer on the connections; and removing the second support wafer.

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.