Patents by Inventor Philippe Coronel

Philippe Coronel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080064174
    Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 13, 2008
    Applicant: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Michel Marty
  • Publication number: 20080017946
    Abstract: An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.
    Type: Application
    Filed: July 20, 2007
    Publication date: January 24, 2008
    Applicants: STMicroelectronics S.A., Commissariat A. L'energie, Atomique, STMicroelectronics Crolles 2 SAS
    Inventors: Yvon Cazaux, Philippe Coronel, Claire Fenouillet-Beranger, Francois Roy
  • Patent number: 7320923
    Abstract: A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable with respect to the second insulating layer; etching the stack, to expose the substrate and keep the stack in the form of a line; forming insulating spacers on the lateral walls of the line; performing an epitaxial growth of a single-crystal semiconductor on the substrate, on either side of the line; selectively removing the third insulating layer to partially expose the second insulating layer at a predetermined location; and depositing and etching a conductive material to fill the cavity formed by the previous removal of the third insulating layer.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 22, 2008
    Assignee: STMicroelectronics Crolles 2 SAS
    Inventors: Bertrand Borot, Philippe Coronel
  • Publication number: 20070278469
    Abstract: A monolithic assembly of electronic components including a semiconductor substrate, at a first level above the substrate, at least one bulk acoustic wave resonator, at a second level above the resonator, a single-crystal semiconductor layer in which are formed semiconductor components, and recesses under the semiconductor layer portions arranged above the resonators.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 6, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Michel Marty, Jean-Christophe Giraudin, Philippe Coronel
  • Publication number: 20070278575
    Abstract: Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.
    Type: Application
    Filed: February 23, 2007
    Publication date: December 6, 2007
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Romain Wacquez, Philippe Coronel, Jessy Bustos
  • Publication number: 20070275513
    Abstract: The invention concerns a method of forming a silicon germanium conduction channel under a gate stack (6) of a semiconductor device, the gate stack being formed on a silicon layer (4) on an insulating layer (2), the method comprising: growing a silicon germanium layer (14) over said silicon layer; and heating the device such that germanium condenses in said silicon layer (4) such that a silicon germanium channel (18) is formed between said gate stack and said insulating layer.
    Type: Application
    Filed: March 5, 2007
    Publication date: November 29, 2007
    Applicant: STMicroelectronics Crolles 2 SAS
    Inventors: Philippe Coronel, Arnaud Pouydebasque
  • Patent number: 7297578
    Abstract: A field effect transistor is produced on a substrate. A semiconductor material is deposited on a portion of a single crystal temporary material. At least part of the temporary material is removed. A portion of a conducting material is then formed above and beneath the portion of semiconductor material. A layer of an electrically insulating material is located between the portion of temporary material and the substrate.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: November 20, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Thomas Skotnicki, Philippe Coronel, Joël Hartmann
  • Publication number: 20070194355
    Abstract: A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.
    Type: Application
    Filed: January 26, 2007
    Publication date: August 23, 2007
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Romain Wacquez, Philippe Coronel, Damien Lenoble, Robin Cerutti, Thomas Skotnicki
  • Publication number: 20070155159
    Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 5, 2007
    Applicants: STMicroelectronics S.A., Commissariat A L'Ernergie Atomique
    Inventors: Philippe Coronel, Yves Laplanche, Laurent Pain
  • Publication number: 20070122975
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 31, 2007
    Applicants: STMicroelectronics Crolles 2 SAS, Commissariat a l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillei-Beranger
  • Patent number: 7214597
    Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: May 8, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Francois Leverd, Thomas Skotnicki
  • Patent number: 7202153
    Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: April 10, 2007
    Assignees: STMicroelectronics S.A., Commissariat a l'Ernergie, Atomique
    Inventors: Philippe Coronel, Yves Laplanche, Laurent Pain
  • Patent number: 7202518
    Abstract: An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain regions. A channel is provided in the intermediate portion of the transistor for each cell. A polarization electrode is placed between the respective intermediate portions of the two transistors. This polarization electrode is capacitively coupled to the intermediate portion of each transistor and is used to store the first and second bits.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: April 10, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Francois Jacquet, Philippe Candellier, Robin Cerutti, Philippe Coronel, Pascale Mazoyer
  • Patent number: 7188411
    Abstract: A process for forming portions of a compound material within an electronic circuit includes the formation of a cavity having at least one opening facing onto an access surface. The cavity furthermore has an internal wall with at least one region made of an initial material (for example, silicon). A metal is deposited close to the region of initial material. The circuit is then heated to form a portion of the compound material (for example, a silicide) in the region of initial material inside the cavity. The compound material is formed from elements of the initial material and from some of the metal deposited. The excess metal that has not formed some of the compound material is then removed from the cavity.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: March 13, 2007
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Christophe Regnier, François Wacquant, Thomas Skotnicki
  • Publication number: 20070037324
    Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.
    Type: Application
    Filed: July 17, 2006
    Publication date: February 15, 2007
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • Publication number: 20070018227
    Abstract: A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
    Type: Application
    Filed: May 15, 2006
    Publication date: January 25, 2007
    Applicant: STMicroelectronics SAS
    Inventors: Philippe Coronel, Romain Wacquez
  • Publication number: 20060286491
    Abstract: An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.
    Type: Application
    Filed: May 26, 2006
    Publication date: December 21, 2006
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique
    Inventors: Jessy Bustos, Philippe Thony, Philippe Coronel
  • Publication number: 20060281031
    Abstract: A method is presented for forming two superposed elements within an integrated electronic circuit. In accordance with the method, a first circuit element, which is reflective with respect to lithography radiation, is formed. A first layer, which is attenuating with respect to lithography radiation, is formed above the first circuit element and includes a first aperture exposing at least a portion of the first circuit element. A second layer, which is transparent with respect to lithography radiation, is formed above the first layer to fill the aperture. A lithography resist layer is then deposited above the second layer and exposed to a radiation flux level below a development threshold of the lithography resist layer but high enough that a sum of the radiation flux level and a secondary radiation flux level reflected from the first circuit element exceeds the development threshold of the lithography resist layer.
    Type: Application
    Filed: May 26, 2006
    Publication date: December 14, 2006
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat a L'Energie Atomique
    Inventors: Jessy Bustos, Philippe Thony, Philippe Coronel
  • Patent number: 7141837
    Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: November 28, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Yves Morand, Thomas Skotnicki, Robin Cerutti
  • Publication number: 20060131667
    Abstract: An SRAM cell with four transistors and two resistors formed in a semiconductor substrate, the transistors being formed in pairs in two active regions of the substrate, the resistors being formed by leakage capacitors, a first electrode of the capacitors being common and formed of a high supply line of the cell buried in an area separating the active regions.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 22, 2006
    Inventors: Bertrand Borot, Philippe Coronel