Abstract: A method is for producing an asymmetric architecture semiconductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.

Abstract: The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: A method for making a transistor with self-aligned gate and ground plane includes forming a stack, on one face of a semi-conductor substrate, the stack including an organometallic layer and a dielectric layer. The method also includes exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of the organometallic portion in said plane. The method also includes removing the exposed part, and forming dielectric portions in empty spaces formed by the removal of the exposed part of the organometallic layer, around the organometallic portion.

Abstract: A gate dielectric, an insulating layer and and an etching mask are formed on a substrate. The etching mask delineates at least the gate electrode and the source and drain contacts and the source, drain and gate output lines of the first metal level of a field effect device. The gate electrode and the future source and drain contacts are formed simultaneously by etching of the insulating layer. A gate material is deposited to form the gate electrode. The source and drain contacts are formed at least in the insulating layer. The source, drain and gate output lines of the first metal level are formed in the etching mask.

Abstract: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.

Abstract: The present invention relates to a method for fabricating a planar independent-double-gate FET or a planar gate-all-around FET on a bulk semiconductor substrate. The method comprises refilling a surface recess in an active semiconductor region with a buried sacrificial layer, and, after preparing a pre-processing a gate stack by respective deposition and patterning, the formation of a recess in the isolation regions so as to cause the recess to extend, in a depth direction that points towards the inner substrate, to a depth level that allows removing the buried sacrificial layer and so as to cause the recess to undercut portions of gate stack in the channel direction.

Abstract: A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.

Abstract: Process for fabricating a transistor, in which an electron-sensitive resist layer lying between at least two semiconductor fingers is formed and said resist lying between at least two wires is converted into a dielectric. For example, in one embodiment of the present disclosure an integrated circuit includes a transistor having an insulating substrate including, for example, based on silicon oxide. Transistor also includes a conducting gate region comprising, for example, TiN or polysilicon, formed on a localized zone of the upper surface of the substrate, and an isolating region, comprising, for example, silicon oxide and surrounding the conducting region. The conducting region is also bounded in the direction normal to the plane of the drawing.

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed.

Abstract: A process for forming a wire portion in an integrated electronic circuit includes epitaxially growing the wire portion on a side surface of a seed layer portion (11, 12). Cross-sectional dimensions of the wire portion correspond to a thickness of the seed layer portion and to a duration of the growing step. The seed layer portion is then selectively removed while the wire portion is retained fixedly on the circuit. Afterwards, heating of the circuit can cause the wire portion becoming rounded in cross-section. The wire portion obtained may be about 10 nanometers in diameter. It may be used for forming a channel of a MOS transistor devoid of short channel effect.

Abstract: A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.

Abstract: A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced.

Abstract: A first circuit element, which is reflective, is formed. A first layer, which is attenuating, is formed. above the first circuit element. A second layer, which is transparent, is formed above the first layer to fill an aperture in the first layer. An overlying lithography resist layer is then exposed to a radiation flux level below a development threshold but high enough that a sum of the radiation flux level and a reflected secondary radiation flux level exceeds the development threshold. The lithography resist layer is developed so as to obtain a mask having an opening through which the first and second layers are removed to form a second aperture which is filled to form a second circuit element.

Abstract: A FinFET (100) comprises a fin-shaped layer-section (116) of a single-crystalline active semiconductor layer (104) extending on an insulating substrate layer (106) along a longitudinal fin direction between, a source layer-section (122), and a drain layer-section (124) of the single-crystalline active semiconductor layer (104). Furthermore, two separate gate-electrode layers (138.1, 138.2) are provided, which do not form sections of the single-crystalline active semiconductor layer, each of the gate-electrode layers facing one of the opposite side faces of the fin-shaped layer-section (116). Each gate-electrode layer is connected with a respective separate gate contact (154, 156).

Abstract: The invention relates to a method for producing stacked and self-aligned components on a substrate, comprising the following steps: forming a stack of layers on one face of the substrate, the stack comprising a first sacrificial layer, a second sacrificial layer and a superficial layer, selective etching of a zone of the first sacrificial layer, the second sacrificial layer and the superficial layer forming a bridge above the etched zone of the first sacrificial layer, depositing resin in the etched zone of the first sacrificial layer and on the superficial layer, lithography of the resin to leave remaining at least one zone of resin in the etched zone of the first sacrificial layer, in alignment with at least one resin zone on the superficial layer, replacing the eliminated resin in the etched zone of the first sacrificial layer and on the superficial layer with a material for confining the remaining resin, eliminating the remaining resin zones in the etched zone of the first sacrificial layer and on the

Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.