Patents by Inventor Philippe Coronel

Philippe Coronel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Back-lit image sensor with a uniform substrate temperature
    Patent number: 7687872
    Abstract: An image sensor including photosensitive cells including photodiodes and at least one additional circuit with a significant heat dissipation including transistors. The image sensor is made in monolithic form and includes a layer of a semiconductor material having first and second opposite surfaces and including, on the first surface side, first regions corresponding to the power terminals of the transistors, the lighting of the image sensor being intended to be performed on the second surface side; a stack of insulating layers covering the first surface; a thermally conductive reinforcement covering the stack on the side opposite to the layer; and thermally conductive vias connecting the layer to the reinforcement.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: March 30, 2010
    Assignees: STMicroelectronics (Crolles) 2 SAS, Commissariat A l'Energie Atomique
    Inventors: Yvon Cazaux, Philippe Coronel, Claire Fenouillet-Béranger, François Roy
  • Component containing a baw filter
    Patent number: 7687833
    Abstract: A monolithic assembly of electronic components including a semiconductor substrate, at a first level above the substrate, at least one bulk acoustic wave resonator, at a second level above the resonator, a single-crystal semiconductor layer in which are formed semiconductor components, and recesses under the semiconductor layer portions arranged above the resonators.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: March 30, 2010
    Assignees: STMicroelectronics S.A., STMicroelectronics Crolles 2 SAS
    Inventors: Michel Marty, Jean-Christophe Giraudin, Philippe Coronel
  • PROCESS FOR PRODUCING A CONTACT PAD ON A REGION OF AN INTEGRATED CIRCUIT, IN PARTICULAR ON THE ELECTRODES OF A TRANSISTOR
    Publication number: 20100025773
    Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 4, 2010
    Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Damien Lenoble, Philippe Coronel, Robin Cerutti
  • Manufacturing method of semiconductor-on-insulator region structures
    Patent number: 7638844
    Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: December 29, 2009
    Assignees: STMicroelectronics S.A., Commissariat à l'énergie atomique
    Inventors: Stéphane Monfray, Aomar Halimaoui, Philippe Coronel, Damien Lenoble, Claire Fenouillett-Beranger
  • SOI TRANSISTOR WITH SELF-ALIGNED GROUND PLANE AND GATE AND BURIED OXIDE OF VARIABLE THICKNESS
    Publication number: 20090311834
    Abstract: Method for making a transistor with self-aligned gate and ground plane, comprising the steps of: a) forming a stack, on one face of a semi-conductor substrate, comprising an organometallic layer and a dielectric layer, b) exposing a part of the organometallic layer, a portion of the organometallic layer different to the exposed part being protected from the electron beams by a mask, the shape and the dimensions of a section, in a plane parallel to the face of the substrate, of the gate of the transistor being substantially equal to the shape and to the dimensions of a section of said organometallic portion in said plane, c) removing the exposed part, d) forming dielectric portions in empty spaces formed by the removal of said exposed part of the organometallic layer, around said organometallic portion.
    Type: Application
    Filed: June 11, 2009
    Publication date: December 17, 2009
    Applicant: COMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Claire FENOUILLET-BERANGER, Philippe CORONEL
  • INTEGRATED CIRCUIT COMPRISING MIRRORS BURIED AT DIFFERENT DEPTHS
    Publication number: 20090256224
    Abstract: A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.
    Type: Application
    Filed: March 5, 2009
    Publication date: October 15, 2009
    Applicant: STMicroelectronics S.A.
    Inventors: Perceval Coudrain, Philippe Coronel, Michel Marty, Matthieu Bopp
  • Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor
    Patent number: 7601634
    Abstract: A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: October 13, 2009
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Damien Lenoble, Philippe Coronel, Robin Cerutti
  • MOS TRANSISTOR MANUFACTURING
    Publication number: 20090224295
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 10, 2009
    Applicants: STMicroelectronics (Crolles) 2 SAS, Commissariat A L'energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • METHOD OF FABRICATING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20090212330
    Abstract: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 27, 2009
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: Emilie Bernard, Bernard Guillaumot, Philippe Coronel
  • METHOD OF MANUFACTURING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20090212333
    Abstract: A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminum is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminum to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 27, 2009
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble) SAS, Commissariat a L'Energie Atomique
    Inventors: Emilie Bernard, Bernard Guillaumot, Philippe Coronel, Christian Vizioz
  • MOS transistor manufacturing
    Patent number: 7556995
    Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: July 7, 2009
    Assignees: STMicroelectronics Crolles 2 SAS, Commissariat a l'Energie Atomique
    Inventors: Philippe Coronel, Claire Gallon, Claire Fenouillet-Beranger
  • METHOD OF PRODUCING AN ASYMMETRIC ARCHITECTURE SEMI-CONDUCTOR DEVICE
    Publication number: 20090093079
    Abstract: A method is for producing an asymmetric architecture semi-conductor device. The device includes a substrate, and in stacked relation, a first photosensitive layer, a non-photosensitive layer, and a second photosensitive layer. The method includes a first step of exposing a first zone in each of the photosensitive layers by a first beam of electrons traversing the non-photosensitive layer. A second step includes exposing at least one second zone of one of the two photosensitive layers by a second beam of electrons or photons or ions, thereby producing a widening of one of the first zones compared to the other first zone such that the second zone is in part superimposed on one of the first zones.
    Type: Application
    Filed: October 2, 2008
    Publication date: April 9, 2009
    Applicant: STMicroelectronics SA
    Inventors: Serdar Manakli, Jessy Bustos, Philippe Coronel, Laurent Pain
  • Method for the formation of an integrated electronic circuit having a closed cavity
    Patent number: 7494932
    Abstract: An integrated electronic circuit includes a cavity buried in a substrate. A surface of the substrate has a depression aligned above the buried cavity. The depression is filled with a material selected so that reflection of a lithography radiation on the substrate surface is attenuated. A resist layer is deposited on the circuit and then exposed to the radiation so that those resist portions which are located above the depression and those located away from the depression receive amounts of radiation that are below and above, respectively, the development threshold of the resist. An etching mask is therefore obtained on the circuit, which is aligned with respect to the cavity and its associated surface depression.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: February 24, 2009
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat a l'Energie Atomique
    Inventors: Jessy Bustos, Philippe Thony, Philippe Coronel
  • IMAGE SENSOR WITH AN IMPROVED SENSITIVITY
    Publication number: 20090014764
    Abstract: An embodiment of an image sensor comprising photosensitive cells, each photosensitive cell comprising at least one charge storage means formed at least partly in a substrate of a semiconductor material. The substrate comprises, for at least one first photosensitive cell, a portion of a first silicon and germanium alloy having a first germanium concentration, possibly zero, and for at least one second photosensitive cell, a portion of a second silicon and germanium alloy having a second germanium concentration, non-zero, greater than the first germanium concentration.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 15, 2009
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS CROLLES 2 SAS
    Inventors: Perceval COUDRAIN, Philippe CORONEL, Xavier BELREDON
  • Method for forming a strongly-conductive buried layer in a semiconductor substrate
    Patent number: 7456071
    Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: November 25, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Michel Marty, Philippe Coronel, François Leverd
  • Realization of Self-Positioned Contacts by Epitaxy
    Publication number: 20080254580
    Abstract: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 16, 2008
    Applicant: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Philippe Coronel, Nicolas Loubet
  • Three-gate transistor structure
    Patent number: 7420253
    Abstract: A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or three transistors having independent respective functions. In particular, the structure may be used as a combination of a transistor with a logic or analog function, with one or two random access memory cells.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2008
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Philippe Coronel, Romain Wacquez
  • ASSEMBLY OF TWO PARTS OF AN INTEGRATED ELECTRONIC CIRCUIT
    Publication number: 20080205027
    Abstract: A process for assembling two parts of an integrated electronic circuit has two successive steps. During a first step, the two circuit parts are made into a single unit by molecular bonding, realized on respective application surfaces of the two parts. During a second step, electrical connections are formed from connection portions already present in the application surfaces of the two circuit parts. The connections formed extend across the bonding interface, and are compatible with a high reliability and a high level of integration of the circuit.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 28, 2008
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Philippe Coronel, Perceval Coudrain, Pascale Mazoyer
  • MOSFET on SOI device
    Publication number: 20080173944
    Abstract: MOSFET on SOI device, comprising: an upper region comprising at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first metallic layer and a first portion of a second semi-conductor layer, a lower region comprising at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one metallic portion, the second semi-conductor layer being arranged on a second dielectric layer stacked on a second metallic layer.
    Type: Application
    Filed: January 18, 2008
    Publication date: July 24, 2008
    Applicants: STMicroelectronics (Crolles 2) SAS,, Commissariat A L'Energie Atomique
    Inventors: Philippe Coronel, Claire Fenouillet-Beranger
  • Manufacturing method of semiconductor-on-insulator region structures
    Publication number: 20080087959
    Abstract: A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.
    Type: Application
    Filed: March 2, 2007
    Publication date: April 17, 2008
    Applicants: STMicroelectronics S.A., Commissariat A L'energie Atomique
    Inventors: Stephane Monfray, Aomar Halimaoui, Philippe Coronel, Damien Lenoble, Claire Fenouillet-Beranger