Abstract: An apparatus for use in a computer has a network interface subsystem having power applied thereto when power is removed from other components of the computer. A receiver in the network interface subsystem receives a packet directed to the computer from the network, and in response to receipt of a selected packet, restores power to the other components of the computer. Upon restoration of power to the other components of the computer, a signalling device reports status of at least one of the other components of the computer to the network interface subsystem. A transmitter in the network interface subsystem sends, in response to the signalling device, a status packet onto the network giving a status of the computer in the event that a component is not functional, following restoration of power to the other components of the computer.

Abstract: A reliable and simple means to awaken sleeping computers is to maintain the network interface subsystem at full power, and to filter detected packets so that when desired packets are detected, full power is restored to the entire computer. An interface to connect a computer to a network is provided, where, the computer has a high power state and a low power state, and the computer is capable of normal operation when in the high power state, and the computer is substantially inactivated when in the low power state. A packet is received from the network. The packet is filtered by computing a hash function using at least one byte selected from the packet. A transition is initiated, responsive to a result of filtering the packet, to transition the computer from the low power state to the high power state. A mask may be used to select the at least one byte. Several bytes may be selected by the mask. A first register may be used to hold the mask.

Abstract: A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely.

Abstract: An apparatus for providing data to an I/O bus at the maximum I/O bus bandwidth comprises an exerciser unit coupled to the I/O device. The exerciser unit includes DMA circuitry for providing a constant stream of transactions to the I/O bus. Each transaction provides a plurality of data quadwords to the I/O bus which are parity protected. The exerciser unit includes a memory device for storing data to be provided for each transaction, and a parity circuit for calculating and providing parity for the data stored in the memory. The exerciser unit further includes a data generation device for providing both data having predictable parity and the parity to the bus for each bus cycle while bypassing the parity generation logic to provide data at maximum bandwidth. The data generation device provides a sequence of different data bytes using a modified Gray-code algorithm, which facilitates parity generation for each byte in the sequence of bytes.

Abstract: The auto-sequenced state machine according to the present invention has a programmable state duration which is independent from the logic speed, it may be adapted to any Moore state machine and may operate in metastability occurrence of the latches (2) of the state machine. The programming of a granularity of half a clock cycle provides a performance optimization by using a system of two clocks which are in opposite phase. Moreover, the state duration may be programmable on line. The auto-sequenced state machine is composed of a basic Moore state machine to which is connected a device (16) comprising a current state decoder (15) which decodes the current state signals Q(t) from the Moore state machine in order to select one of the biphase state timers (13) and one of the state timing programming circuits (12), and an OR circuit (11) which receives the terminal counts (TC0, . . .

Abstract: The arbitrating method is based on the classification of the users into different categories, and the assignment to all users in a category of an identical privilege level which characterizes the interruption capability of the users in the category. A task performed by a selected user in a category can only be interrupted for granting access to the resource to a user in a category having a higher privilege level. Also a normal preference level is assigned to each user within a category, which determines the selection order of the users in the category. The privilege level of a user category combined with the preference level of each user constitutes the priority level of the user. The access to the resource is granted to a selected user having the highest priority level.

Abstract: The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N B-bit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix which gives the capability of only correcting one block in error and improving the memory failure rate by cyclically reading each word, correcting a block found in error if any and writing the corrected data bits with the corresponding error correction bits in place of the read word.

Abstract: Synchronization apparatus in interconnected units of a data processing system resynchronize received bits from a bus with the internal clock of the unit. The synchronization arrangement has two identical synchonization devices which alternately process received strobe pulses which are used for sampling data bits into a first register, generating a gating pulse on one output and a validation pulse on a second output. In response to the gating pulse, bits stored in the first register are transferred to a second register to be available for use by processing logic in synchronism with the internal clock signal. The synchronization devices include two parallel synchronization circuits operating in opposite phase so that the detection of one strobe pulse by one circuit: automatically disables the other one.