Abstract: A method of forming junction isolation to isolate active elements. A substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first and the second gate structures. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Part of the bottom anti-reflection layer is etched to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving as a junction isolation region is formed in the substrate located in the isolation area.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern are partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: A method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereof. A gate structure is formed on a substrate. Diffusion regions are formed in the substrate on either side of the gate structure. A linear oxide layer is formed on the gate structure and the substrate. A conformal nitride layer is formed on the linear oxide layer. The nitride layer and the linear oxide layer are partially etched back to form linear oxide spacers on the sides of the gate structure and nitride spacers on the sides of the linear oxide spacers. A conformal oxide layer is formed on the linear oxide spacers, the nitride spacers, the gate structure and the substrate. The oxide layer is partially etched back to form oxide spacers on the sides of the nitride spacers.

Abstract: A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation structure over the surface of the interconnect structure. The passivation structure comprises a dielectric layer over the surface of the interconnect structure and a silicon-oxy-nitride (SiOxNy) layer over the surface of the dielectric layer.

Abstract: The present invention is directed to polynucleotides encoding polypeptides associated with the development of osteoarthritis and homologs thereof. The invention further relates to diagnostic and therapeutic methods for utilizing these polynucleotides and polypeptides in the diagnosis, treatment, and/or prevention of osteoarthritis and related disease states. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, and compounds identified thereby.

Abstract: The present invention is directed to polynucleotides encoding polypeptides associated with the development of rheumatoid arthritis and homologs thereof. The invention further relates to diagnostic and therapeutic methods for utilizing these polynucleotides and polypeptides in the diagnosis, treatment, and/or prevention of rheumatoid arthritis and related disease states. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, and compounds identified thereby.

Abstract: A facility for improving the environmental atmosphere of an interior space, which includes a negative ion discharger; a plurality of electric poles connected to the output wires of the negative ion discharger. The aforementioned negative ion discharger is placed in a corner of the interior space, and the plurality of electric poles are situated in the upper part of the interior space. By means of an active carbon layer beneath the floor indoors, an invisible shelter will be formed by the negative ions released from the negative ion discharger. Accordingly, the ion energy will be effectively decreased, and the particle condition of the indoor space will be harmonized.

Abstract: A method of eliminating weakness caused by high-density plasma (HDP) dielectric layer is provided. Before forming the HDP dielectric layer, a hot thermal oxide (HTO) layer is previously formed on the semiconductor substrate to serve as a buffer layer. The HTO layer eliminates the defect between the HDP dielectric layer and a cap nitride layer and releases the stress therebetween, and thereby preventing bit line leakage issue.

Abstract: A method and an integrated circuit for performing a soft program after erase provides efficient convergence of over-erased floating gate memory cells disposed in bit lines. The soft program is applied to successive subject bit lines. The BLISP method includes selection of a selected bit line and applying the soft program to a subject bit line corresponding to the selected bit line. For integrated circuits having no defective bit lines, the subject bit lines comprise the selected bit lines. The BLISP method is adapted for low current consumption compared to bulk soft programming methods. In some embodiments, the integrated circuit includes defective bit lines. For these integrated circuits, the selection of the selected bit line includes indicating a bit line type corresponding to the selected bit line. The defective bit lines are logically replaced by redundant bit lines so that the soft program is applied to conforming selected bit lines and redundant bit lines corresponding to defective bit lines.

Abstract: A process for planarization of a flash memory cell is described. A first polysilicon pattern having a top is formed over a substrate. A high-density plasma (HDP) oxide layer is deposited on the first polysilicon pattern, wherein the HDP oxide layer has a protuberance over the first polysilicon pattern. The HDP oxide layer and the first polysilicon pattern is partially etched by a sputtering etch technology. In this etching step, the protuberance is removed, the first polysilicon pattern is lowered, and the top of the first polysilicon pattern is rounded. A second polysilicon pattern covering the first polysilicon pattern is formed, wherein the second polysilicon pattern is wider than the first polysilicon pattern.

Abstract: A method for forming a plurality of contact openings on a semiconductor substrate using an etch stop layer is disclosed herein. A semiconductor substrate is provided having a plurality of memory devices and a plurality of isolation regions formed thereon. A silicon oxide layer is formed on the plurality of semiconductor devices, the plurality of isolation regions, and the semiconductor substrate. An etch stop layer is formed on the silicon oxide layer followed by depositing a thick interlevel dielectric layer. A photoresist layer is pattern on the interlevel dielectric layer to define contact regions. A first dry etching process is performed to create a plurality of contact openings with different dimension in the interlevel dielectric layer until exposing portions of the etch stop layer. A second dry etching process is performed to create the plurality of contact openings through the etch stop layer.

Abstract: The present invention provides nucleic acids encoding B7-related factors that modulate the activation of immune or inflammatory response cells, such as T-cells. Also provided are expression vectors and fusion constructs comprising nucleic acids encoding B7-related polypeptides, including BSL1, BSL2, and BSL3. The present invention further provides isolated B7-related polypeptides, isolated fusion proteins comprising B7-related polypeptides, and antibodies that are specifically reactive with B7-related polypeptides, or portions thereof. In addition, the present invention provides assays utilizing B7-related nucleic acids, polypeptides, or peptides. The present invention further provides compositions of B7-related nucleic acids, polypeptides, fusion proteins, or antibodies that are useful for the immunomodulation of a human or animal subject.

Abstract: A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.

Abstract: A barbecue tool device comprises a handle with a lateral orifice for engagingly receiving a locking device and one or more tool metal heads having a shank slidable movable in the handle. The shanks of tool metal head comes with a pair of side walls having two or more notches each. The locking device includes a pair of catches engagingly received in the orifices and a spring sitting between the two catches for pushing the catches into the notches of the shank to be locked with the handle, the catches have a slot each for receiving the side walls of the shank and allowing the tool metal head to travel freely in the handle. The tool device may consist of a number of tool metal heads having a shank for selectively engaging with the handle when required.

Abstract: The frequency of an integrated oscillator is held constant by using temperature compensation to compensate for the component variations due to temperature variations. A voltage controlled oscillator, which has temperature dependent components, is compensated with a temperature dependent control voltage. The frequency of many kinds of oscillators such as a relaxation oscillators and ring oscillators can be held constant when the operating current is held constant. The operating current is often derived from a current source, which is a voltage to current converter with a current equal to the ratio of a control voltage to a resistance. Since semiconductor resistance has a positive temperature coefficient is used to obtain a temperature invariant current source. The positive temperature coefficient is obtained with the difference junction voltage of two forward-biased pn junction voltages. The magnitude can be controlled by junction areas of the two junctions. The magnitude can also be amplified.