Abstract: A method of manufacturing a nano-crystalline silicon dot layer is provided. A silicon layer is formed over a substrate. The silicon layer includes crystalline silicon region and amorphous silicon region. An oxidation process is performed to oxidize the amorphous silicon region and the surfaces of the crystalline silicon region to form a silicon oxide layer containing nano-crystalline silicon dots.

Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.

Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.

Abstract: A method for assisting in focal length detection is applicable to a digital camera having the flash. The method includes the following steps. First, the flash of the digital camera is actuated and a first image is captured. Afterwards, a characteristic exposure value of the first image is calculated. A focus range comparison table is looked up according to the characteristic exposure value to obtain an initial focus position. Then, a focus procedure is performed according to the initial focus position to obtain a target focal length.

Abstract: An arrangement for securing a wafer during substrate processing is provided. The arrangement includes a power supply and an electrostatic chuck (ESC). The ESC supports the wafer and includes a positive and a negative terminal. A positive high voltage is provided to the positive terminal through an RF filter and a negative high voltage is provided to the negative terminal through the RF filter. The arrangement also includes a first and a second trans-impedance amplifiers (TIAs) that measure a first set of voltages for determining a value of a positive load current applied to the positive terminal and a third and fourth TIAs that measure a second set of voltages for determining a value of a negative load current applied to the negative terminal. The arrangement yet also includes a program to adjust a bias voltage using the values of the positive load current and the negative load current.

Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.

Abstract: A method for assist in focal length detection is adapted to a digital camera having a flash. The method includes the following steps. First, the flash of the digital camera is actuated and an image having a face portion is captured. Afterwards, an exposure feature value of the face portion in the image is calculated. A focus range comparison table is looked up according to the exposure feature value to obtain an initial focus position. Then, a focus procedure is performed according to the initial focus position to obtain a target focal length. After the target focal length is obtained, a flash feature value of the image is further calculated, and a guide number (GN) and a diaphragm value are set according to the flash feature value.

Abstract: A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.

Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.

Abstract: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.

Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.

Abstract: A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.

Abstract: A method of forming a contact on a semiconductor device is provided. First, a substrate is provided. A plurality of gate structures defined by a plurality of word lines in a first direction, and a plurality of diffusion regions covered by a first dielectric layer in a second direction are provided over the substrate. The gate structures located underneath the word lines and isolated by the diffusion regions. Then, an etching stop layer is formed. The etching stop layer and the first dielectric layer have different etching selectivity. A second dielectric layer is formed over the substrate. Furthermore, a plurality of contact holes to the diffusion regions between the word lines are formed by using the etching stop layer as a self-aligned mask.

Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.

Abstract: A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (?ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.

Abstract: A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.

Abstract: An adjusting method of flash intensity is applied in an image capture apparatus with a flash lamp, where two pre-flash images corresponding the object are retrieved under two different pre-flash lights, respectively, and then a flash intensity of main-flash light is calculated according to one of the retrieved pre-flash images, so as to retrieve a main-flash image corresponding the object under the main-flash light with the calculated main-flash light.

Abstract: A digital image capture device and a brightness correction method thereof are described. The digital image capture device is adapted to correct the brightness value of a shot object in a digital image through the compensation of a strobe during shooting. The method includes setting a shooting magnification of the digital image capture device to the shot object; capturing a pre-shot image at least including the image of the shot object; triggering a strobe to emit a main flash onto the shot object, so as to shoot a digital image; setting a plurality of light measuring areas in the digital image; calculating a corresponding object distance of the shot object from each of the light measuring areas; establishing a shading table according to each of the object distances; and loading the shading table to adjust the brightness value of each of the light measuring areas in the digital image.

Abstract: The present invention is directed to polynucleotides encoding polypeptides associated with the development of rheumatoid arthritis and homologs thereof. The invention further relates to diagnostic and therapeutic methods for utilizing these polynucleotides and polypeptides in the diagnosis, treatment, and/or prevention of rheumatoid arthritis and related disease states. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, and compounds identified thereby.

Abstract: An image brightness correction method is described. First, a pre-flash is fired and a pre-flash image is shot. After a main flash duration is estimated according to the pre-flash image and an automatic exposure time of a camera device, a main flash is fired and a raw image is shot. Then, a brightness gain of the raw image is compensated according to a preset gain threshold, and a digital brightness gain of the image is adjusted to enable the image shot each time to achieve the same brightness gain.