Abstract: An image brightness compensation method and a digital camera device with an image brightness compensation function are suitable for adjusting a brightness of a digital image shot by a digital camera device, especially when the shot object is located outside a maximum output range of a flash lamp. The method includes the steps of pre-capturing a target image, and recording target information; triggering a flash lamp, and meanwhile capturing a raw image; determining whether the raw image satisfies a brightness threshold or not according to a brightness difference between the target information and the raw image; if the raw image fails to satisfy the brightness threshold, executing a brightness compensation program on the raw image according to the target information; and finally, generating an output image.

Abstract: A method of fabricating a non-volatile memory is provided. First, a bottom oxide layer is formed on a substrate. Thereafter, a silicon-rich nitride layer is formed on the bottom oxide layer by using NH3 and SiH2Cl2 or SiH4, wherein the thickness of the silicon-rich nitride layer is less than about 40 ?, and the gas flow ratio of NH3 to SiH2Cl2 or SiH4 is about 0.2-0.5. Afterwards, a top oxide layer is formed on the silicon-rich nitride layer. Further, a gate is formed on the top oxide layer. Two doped regions are then formed in the substrate beside the gate.

Abstract: The present invention is directed to polynucleotides encoding polypeptides associated with the development of rheumatoid arthritis and homologs thereof. The invention further relates to diagnostic and therapeutic methods for utilizing these polynucleotides and polypeptides in the diagnosis, treatment, and/or prevention of rheumatoid arthritis and related disease states. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, and compounds identified thereby.

Abstract: Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+?VD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: Methods for forming a pattern layer over a target layer are disclosed. The methods use a novel low temperature spacer structure which results in a pattern layer having a decreased pattern pitch versus conventional patterning using photolithography. The decreased pattern pitch allows the target layer to be divided into multiple regions separated by a small distance, which in turn allows for greater density and device miniaturization. The structure and methods may be applied to patterning a word line layer in a memory device.

Abstract: A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.

Abstract: A method for video conversion of a video stream includes: interpolating a first interpolated frame according a first frame and a second frame of the video stream; and interpolating a second interpolated frame according to the first frame and the first interpolated frame. In addition, the method further includes interpolating a third interpolated frame according to the second frame and the first interpolated frame.

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer.

Abstract: The present invention is directed to polynucleotides encoding polypeptides associated with the development of rheumatoid arthritis and homologs thereof. The invention further relates to diagnostic and therapeutic methods for utilizing these polynucleotides and polypeptides in the diagnosis, treatment, and/or prevention of rheumatoid arthritis and related disease states. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention, and compounds identified thereby.

Abstract: A plasma processing system is disclosed. The plasma processing system may include an electrostatic chuck (ESC) positioned inside a plasma processing chamber and configured to support a wafer. The ESC may include a positive terminal (+ESC) for providing a first force to the wafer and a negative terminal (?ESC) for providing a second force to the wafer. The plasma processing system may also include a first trans-impedance amplifier (TIA) and a second TIA configured to measure a first set of voltages for calculating a value of a positive load current applied to the positive terminal. The plasma processing system may also include a third TIA and a fourth TIA configured to measure a second set of voltages for calculating a value of a negative load current applied to the negative terminal.

Abstract: An adaptive de-interlacer can convert an interlaced video signal into a progressive video signal, and comprises a motion detector, an intra-field interpolator, an inter-field interpolator, a motion aliasing artifact detector and a blending unit. The motion detector generates an alpha value for each interpolated pixel in a current field of the interlaced video signal based on successive fields of the interlaced video signal. The intra-field interpolator outputs an intra-field interpolated pixel based on the current field, and the inter-field interpolator also outputs an inter-field interpolated pixel based on the successive fields. Afterward, the motion aliasing artifact detector detects whether the interpolated pixel is located in a motion aliasing area.

Abstract: An adaptive de-interlacer can convert an interlaced video signal into a progressive video signal, and comprises an intra-field interpolator, an inter-field interpolator, a static pixel detector, a motion detector and a blending unit. The intra-field interpolator outputs an intra-field interpolated pixel based on a current field of the interlaced video signal, and the inter-field interpolator outputs an inter-field interpolated pixel based on successive fields of the interlaced video signal. The static pixel detector detects whether each interpolated pixel is a static pixel based on luminance differences between pixels of the successive fields with reference to a threshold and outputs a detection result. The motion detector generates a motion value for the interpolated pixel based on the successive fields and the detection result.

Abstract: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.

Abstract: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.