Patents by Inventor Ping Chen

Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200026999
    Abstract: Methods and systems are disclosed for boosting deep neural networks for deep learning. In one example, in a deep neural network including a first shallow network and a second shallow network, a first training sample is processed by the first shallow network using equal weights. A loss for the first shallow network is determined based on the processed training sample using equal weights. Weights for the second shallow network are adjusted based on the determined loss for the first shallow network. A second training sample is processed by the second shallow network using the adjusted weights. In another example, in a deep neural network including a first weak network and a second weak network, a first subset of training samples is processed by the first weak network using initialized weights. A classification error for the first weak network on the first subset of training samples is determined.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 23, 2020
    Inventors: Libin Wang, Yiwen Guo, Anbang Yao, Dongqi Cai, Lin Xu, Ping Hu, Shangong Wang, Wenhua Cheng, Yurong Chen
  • Publication number: 20200027015
    Abstract: Described herein are systems and methods for providing deeply stacked automated program synthesis. In one embodiment, an apparatus to perform automated program synthesis includes a memory to store instructions for automated program synthesis and a compute cluster coupled to the memory. The compute cluster supports the instructions for performing the automated program synthesis including partitioning sketched data into partitions, training diverse sets of individual program synthesis units each having different capabilities with partitioned sketched data and for each partition applying respective transformations, and generating sketched baseline data for each individual program synthesis unit.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 23, 2020
    Inventors: Angang YAO, Dongqi CAI, Libin WANG, Lin XU, Ping HU, Shandong WANG, Wenhua CHENG, Yiwen GUO, Liu YANG, Yurong CHEN, Yuqing HOU, Zhou SU
  • Publication number: 20200022582
    Abstract: An image-processing method for marking plaque fluorescent reaction areas is provided, including: obtaining a first RGB image of a mouth region; obtaining a second RGB image of the mouth region; respectively converting the first RGB image and the second RGB image into a first HSV image and a second HSV image; obtaining a first average brightness value of the first HSV image and a second average brightness value of the second HSV image; normalizing the first average brightness value or the second average brightness value according the first average brightness value and the second average brightness value to obtain a normalized image; converting the normalized image into a third RGB image, and obtaining a plurality of pixel points of the dental plaque according to the third RGB image and the first RGB image or the second RGB image; and marking the pixel points in the third RGB image.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 23, 2020
    Inventors: Kai-Ju Cheng, Chin-Yuan Ting, Hsin-Lun Hsieh, Tsung-Hsin Lu, Yu-Hsun Chen, Hao-Ping Lee
  • Publication number: 20200026965
    Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 23, 2020
    Inventors: Yiwen GUO, Yuqing Hou, Anbang Yao, Dongqi Cai, Lin Xu, Ping Hu, Shangong Wang, Wenhua Cheng, Yurong Chen, Libin Wag
  • Publication number: 20200026988
    Abstract: Methods and systems are disclosed using improved training and learning for deep neural networks. In one example, a deep neural network includes a plurality of layers, and each layer has a plurality of nodes. For each L layer in the plurality of layers, the nodes of each L layer are randomly connected to nodes in a L+1 layer. For each L+1 layer in the plurality of layers, the nodes of each L+1 layer are connected to nodes in a subsequent L layer in a one-to-one manner. Parameters related to the nodes of each L layer are fixed. Parameters related to the nodes of each L+1 layers are updated, and L is an integer starting with 1. In another example, a deep neural network includes an input layer, output layer, and a plurality of hidden layers. Inputs for the input layer and labels for the output layer are determined related to a first sample. Similarity between different pairs of inputs and labels between a second sample with the first sample is estimated using Gaussian regression process.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 23, 2020
    Inventors: Yiwen Guo, Anbang Yao, Dongqi Cai, Libin Wang, Lin Xu, Ping Hu, Shangong Wang, Wenhua Cheng, Wenhua Cheng, Yurong Chen
  • Patent number: 10540318
    Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: January 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Farshad Akhbari, Feng Chen, Dukhwan Kim, Narayan Srinivasa, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu
  • Patent number: 10541035
    Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: January 21, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai, Yingda Dong
  • Publication number: 20200020841
    Abstract: A method of manufacturing a hexagonal boron nitride (hBN) laminate on a backside of LED filament contains steps of: a) Preparing a substrate of LED filament array; b) Coating the hBN based slurry on the backside of substrate of LED filament and dried at 100-200° C.; c) Cutting the array to single LED filament. A LED filament with hBN based heat dissipation radiation laminate was obtained after this process. For heat dissipation application, hexagonal boron nitride laminate coating can significantly enhance the performance of LED light bulb.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventors: Jingyu ZHANG, Kuo-Hsin CHANG, Jia-Cing CHEN, Chung-Ping LAI
  • Publication number: 20200016635
    Abstract: A photoresist removal method is provided. The photoresist removal method includes analyzing the process status of each of a number of semiconductor substrate models undergoing a tested plasma ash process by a residue gas analyzer. The tested plasma ash processes for the semiconductor substrate models utilize a plurality of tested recipes. The photoresist removal method further includes selecting one of the tested recipes as a process recipe based on the analysis results from the residue gas analyzer and at least one expected performance criterion. In addition, the photoresist removal method includes performing a plasma ash process on a semiconductor substrate according to the process recipe to remove a photoresist layer from the semiconductor substrate.
    Type: Application
    Filed: July 4, 2019
    Publication date: January 16, 2020
    Inventors: Chun-Jen HSIAO, Ya-Ping CHEN, Chien-Hung LIN, Wen-Pin LIU, Chin-Wen CHEN
  • Publication number: 20200020837
    Abstract: The invention provides a light emitting chip comprising a conductive carrier, a semiconductor layer body having a first semiconductor layer, a second semiconductor layer, and a radiation emitting layer, wherein the semiconductor layer has a concave part extending from the surface of the first semiconductor layer through the radiation emitting layer toward the second semiconductor layer; a first electrical connection layer electrically connected between the first semiconductor layer and the first electrode; a second electrical connection layer electrically connected between the second semiconductor layer and the conductive carrier, wherein the second electrical connection layer includes a continuous electrode structure connected to the second semiconductor layer, the continuous electrode structure being constituted by at least a frame structure distributed at the edge of the light emitting chip; and a second electrode electrically connected to the conductive carrier.
    Type: Application
    Filed: September 20, 2018
    Publication date: January 16, 2020
    Applicant: High Power Opto, Inc.
    Inventors: Li-Ping Chou, Wan-Jou Chen, Wei-Yu Yen
  • Publication number: 20200021182
    Abstract: An inverter apparatus with overcurrent protection control includes a first terminal of a DC input terminal connected to an AC output terminal through a first switch element and a second switch element, and a second terminal of the DC input terminal connected to the AC output terminal through a fourth switch element and a third switch element. An intermediate potential terminal is connected to a fifth switch element and a sixth switch element, and connected to the AC output terminal through the fifth switch element and the second switch element, and connected to the AC output terminal through the sixth switch element and the third switch element. When the control unit determines that the inverter apparatus is in an overcurrent state, the control unit controls a sequence of turning off the inverter apparatus to be the second switch element, the first switch element, and the sixth switch element.
    Type: Application
    Filed: January 3, 2019
    Publication date: January 16, 2020
    Inventors: Chao-Li KAO, Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Chao-Lung KUO, Po-Hsin TSENG, Hong-Wen CHEN
  • Publication number: 20200020070
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 8-bit and/or 32 bit signed or unsigned integer elements.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Linda L. Hurd, Dukhwan Kim, Mike B. Macpherson, John C. Weast, Feng Chen, Farshad Akhbari, Narayan Srinivasa, Nadathur Rajagopalan Satish, Joydeep Ray, Ping T. Tang, Michael S. Strickland, Xiaoming Chen, Anbang Yao, Tatiana Shpeisman
  • Patent number: 10534272
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 10534833
    Abstract: A method of Webpage navigation can include a computer device loading a Webpage having at least a first portion and a second portion, arranging the Webpage in order to present the first portion in the display area of the computer device and to place the second portion out of the display area, and presenting a navigation map corresponding to the Webpage in the display area. In response to a control command input with respect to the navigation map, the Webpage can be arranged in order to present the second portion in the display area.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Ju Chen, John J. Y. Hsu, Bor-Ping Pan, Rick M. F. Wu
  • Publication number: 20200013949
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
    Type: Application
    Filed: August 7, 2018
    Publication date: January 9, 2020
    Inventors: Ya-Sheng Feng, Hung-Chan Lin, Yu-Ping Wang, Yu-Chun Chen, Chiu-Jung Chiu
  • Publication number: 20200014353
    Abstract: An automatic gain control circuit for controlling an LNA for inputting signals carrying packets, the automatic gain control circuit can perform a background calibration in the non-preamble time region of a first packet for pre-determining a gain adjustment to the LNA before the next preamble of a second packet arrives, so that the gain of the LNA can be adjusted immediately according to the pre-determined gain adjustment when the next preamble of the second packet arrives.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Meng-Ping Kan, Kuan-Ming Chen, Benjamin Chiang, Tzy-Yun Wang
  • Publication number: 20200015163
    Abstract: A first device obtains an advertising parameter used by a second device to send an advertising data packet, where the advertising parameter includes an advertising window and an advertising interval. The first device determines, based on the advertising window and the advertising interval by using a preset scanning model, a target scan parameter used by the first device, where the target scan parameter is a scan parameter used by the first device when power consumption of the first device is a preset threshold and a scan-to-discover time period satisfies a preset condition. The target scan parameter includes a target scan window and a target scan interval. The first device performs scanning based on the target scan window and the target scan interval.
    Type: Application
    Filed: March 14, 2017
    Publication date: January 9, 2020
    Inventors: Jun Yang, Xiyu Zhou, Jian Chen, Ya Zhang, Jiaxin Li, Bingjian Du, Yeqin Zhang, Ping Wei, Zhiqiang Zhang
  • Patent number: 10528675
    Abstract: A method for context-aware translation is provided. The present invention may include receiving a program integrated information file (PII) associated with a graphical user interface object of with a software product. The present invention may also include indexing each element string within the PII file. The present invention may further include generating a base language general availability build of the graphical user interface object using the PII file. The present invention may also include retrieving a document object model (DOM) of each element within the base language general availability build. The present invention may further include creating a string relation table for the base language general availability build using the DOM for each element and each indexed element string within the PII file. The present invention may also include generating a string relation translation memory table for at least one language.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chi-Ying Chang, Yi-Chun Chen, Wen-Ping Chi, Chao Yuan Huang
  • Patent number: 10529920
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Hung-Chan Lin, Yu-Ping Wang, Yu-Chun Chen, Chiu-Jung Chiu
  • Publication number: 20200005878
    Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Han-Ping Chen, Chung-Yao Pai, Yingda Dong