Patents by Inventor Ping Chen
Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250118598Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.Type: ApplicationFiled: October 4, 2023Publication date: April 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Shao-Kuan LEE, Kuang-Wei YANG, Gary HSU WEI LIU, Yen-Ju WU, Jing-Ting SU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
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Patent number: 12269975Abstract: A composite film includes a first thermoplastic elastomer film layer and a second thermoplastic elastomer film layer, wherein the first thermoplastic elastomer film layer includes a first styrenic block copolymer. The second thermoplastic elastomer film layer is disposed on the first thermoplastic elastomer film layer, wherein the second thermoplastic elastomer film layer includes a second styrenic block copolymer, diffusion particles dispersed in the second thermoplastic elastomer film layer, and a surface microstructure disposed on the surface of the second thermoplastic elastomer film layer.Type: GrantFiled: April 27, 2023Date of Patent: April 8, 2025Assignee: Industrial Technology Research InstituteInventors: Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang, Yi-Ping Chen
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Publication number: 20250112087Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
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Publication number: 20250112088Abstract: A semiconductor structure is provided. The semiconductor structure includes a first low dielectric constant (low-k) layer, a first metal layer, a metal cap layer, a dielectric on dielectric (DoD) layer, an etch stop layer (ESL), a second low-k layer, a metal via and a second metal layer. The dielectric constant of the first low-k layer is less than 4. The first metal layer is embodied in the first low-k layer. The first low-k layer exposes the first metal layer. The metal cap layer is disposed on the first metal layer. The DoD layer is disposed on the first low-k layer. The etch stop layer is disposed on the metal cap layer and the DoD layer. The second low-k layer is disposed above the etch stop layer. The metal via is embodied in the second low-k layer and connected to the first metal layer.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chin LEE, Yen Ju WU, Shao-Kuan LEE, Kuang-Wei YANG, Hsin-Yen HUANG, Jing Ting SU, Kai-Fang CHENG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
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Patent number: 12266715Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: GrantFiled: August 10, 2023Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
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Patent number: 12266922Abstract: A circuit for reverse battery protection includes an isolation circuit and a control circuit. The isolation is circuit coupled between a gate output of an electronic fuse (E-fuse) and at least one external metal-oxide-semiconductor field-effect transistor (MOSFET). The E-fuse is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller. The isolation circuit is configured to disconnect the gate output from the at least one external MOSFET when the battery is installed with reverse polarity. The control circuit is coupled between the external ground pin and the at least one external MOSFET. The control circuit is configured to turn on the at least one external MOSFET when the battery is installed with the reverse polarity.Type: GrantFiled: June 20, 2022Date of Patent: April 1, 2025Assignees: STMicroelectronics S.r.l., STMicroelectronics (China) Investment Co., Ltd.Inventors: Ping Chen, Hui Yan, Vincenzo Randazzo, Alberto Marzo, Andrea Camillo Re
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Patent number: 12267772Abstract: Embodiments of the present disclosure relate to a method and an apparatus for managing network slice for terminal device. A first aspect of the present disclosure provides a method performed at a server function, comprising: determining to change a network slice for a terminal device; and transmitting, to an exposure function, a request to change the network slice for the terminal device. According to embodiments of the present disclosure, a server may be able to change the network slice for a terminal device.Type: GrantFiled: May 12, 2020Date of Patent: April 1, 2025Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Cheng Wang, Ping Chen, Xiao Li, Huiwei Zheng
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Patent number: 12264134Abstract: Disclosed herein are compounds of formula (I) which are inhibitors of an IDO enzyme: (I). Also disclosed herein are uses of the compounds in the potential treatment or prevention of an IDO-associated disease or disorder. Also disclosed herein are compositions comprising these compounds. Further disclosed herein are uses of the compositions in the potential treatment or prevention of an IDO-associated disease or disorder.Type: GrantFiled: November 25, 2019Date of Patent: April 1, 2025Assignee: Merck Sharp & Dohme LLCInventors: Dane Clausen, Ping Chen, Xavier Fradera, Liangqin Guo, Yongxin Han, Shuwen He, Xianhai Huang, Joseph Kozlowski, Guoqing Li, Theodore A. Martinot, Alexander Pasternak, Andreas Verras, Li Xiao, Feng Ye, Wensheng Yu, Rui Zhang
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Publication number: 20250102852Abstract: A display screen applied to a display device is provided. The display screen includes a cover plate structure and a backlight structure. The cover plate structure includes a cover plate layer and an optical coating layer. The optical coating layer comprises an anti-glare (AG) layer on a surface of the cover plate layer. The backlight structure is located on another surface opposite to the AG layer on the cover plate layer. The backlight structure includes a first diffusion layer and a second diffusion layer stacked on the first diffusion layer.Type: ApplicationFiled: November 11, 2022Publication date: March 27, 2025Applicant: HUIZHOU TCL MOBILE COMMUNICATION CO., LTD.Inventors: Jitao MA, Zhuwei QIU, Ping CHEN, Panwei XIONG, Yang YU
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Publication number: 20250098751Abstract: The present invention discloses an electronic aerosol generation device and atomizer thereof, the atomizer comprises a shell, a fixing component, and an atomizing component. The atomizing component comprises a liquid conducting member and a heating element. The liquid conducting member is provided with an air guide hole running through itself longitudinally, and a liquid guide groove. The liquid guide groove may include a first sub-liquid guide groove and a second sub-liquid guide groove in communication with the first sub-liquid guide groove. The first sub-liquid guide groove is in communication with a liquid guide channel. The aerosol generated by the atomizing component can directly enter the air guide tube through the air guide hole, with a short flow path. The liquid conducting member injects liquid from the top, which is less prone to oil and liquid leakage compared to injecting liquid from the side.Type: ApplicationFiled: September 11, 2024Publication date: March 27, 2025Inventor: Ping Chen
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Publication number: 20250104778Abstract: An operation method of a memory device including the following operations is provided. Applying a read voltage to a selected page of a plurality of programmed memory pages. Applying a first pass voltage to unselected pages of the plurality of programmed memory pages. Applying a second pass voltage to at least one unprogrammed memory page, wherein the first pass voltage is larger than the second pass voltage. A memory system including a 3D NAND flash memory with high capacity and high performance is also provided.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Applicant: MACRONIX International Co., Ltd.Inventors: Che-Ping Chen, Ya-Jui Lee
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Publication number: 20250098761Abstract: The invention discloses an atomization device and atomization core thereof, the atomization core comprises a liquid conducting member and a heating element. The liquid conducting member is provided with an airflow hole running through itself longitudinally, and at least one liquid storage groove. The liquid storage groove is located on the outer periphery of the airflow hole, and the liquid storage groove includes at least one first sub-liquid storage groove and at least one second sub-liquid storage groove in communication with the first sub-liquid storage groove. The airflow hole is located at the center of the liquid conducting member, which can be close to the outlet of the atomization device, the aerosol generated by the atomization core has a shorter flow path and is less prone to affect the taste due to cooling, and it can effectively prevent the aerosol from condensing due to cooling during the flow process.Type: ApplicationFiled: September 11, 2024Publication date: March 27, 2025Inventor: Ping Chen
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Patent number: 12256782Abstract: A heating device and a manufacturing method therefor, and a heat-not-burn smoking device. The heating device includes a first heating assembly, including a first housing configured for contacting with a tobacco, a first heating element on the first housing and configured to generate heat when electrified, and a first insulator between the first heating element and the first housing. The first heating element generates heat when electrified, the heat is conducted to the first housing through the first insulator, to heat but not burn the tobacco. The heating device is formed by cooperation of the heating element, the insulator and the housing, and heats the tobacco by the heating element when electrified. Compared with a heating conductive layer formed by a thick film printing process, the manufacturing of the heating device is simpler and more convenient, and the consistency and service life of the product are greatly improved.Type: GrantFiled: May 19, 2020Date of Patent: March 25, 2025Assignee: Shenzhen Huachengda Precision Industry Co. Ltd.Inventor: Ping Chen
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Patent number: 12261213Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.Type: GrantFiled: July 25, 2022Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Patent number: 12256202Abstract: The invention discloses a stereo enhancement system and a stereo enhancement method. The stereo enhancement system includes a beamforming unit and a signal processing unit. The beamforming unit is used for receiving a plurality of input sound signals and generating a plurality of beamforming sound signals corresponding to a plurality of direction intervals respectively. The signal processing unit is coupled to the beamforming unit and used for receiving the plurality of beamforming sound signals corresponding to the plurality of direction intervals respectively and generating a first synthesized output sound signal and a second synthesized sound signal accordingly.Type: GrantFiled: December 7, 2022Date of Patent: March 18, 2025Assignee: INTELLIGO TECHNOLOGY INC.Inventors: Chia-Ping Chen, Chih-Sheng Chen, Hua-Jun Hong, Chien-Hua Hsu, Jen-Feng Li, Wei-An Chang, Tsung-Liang Chen
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Patent number: 12251081Abstract: A cavity interposer has a cavity, first bondpads adapted to couple to a chip-type camera cube disposed within a base of the cavity at a first level, the first bondpads coupled through feedthroughs to second bondpads at a base of the interposer at a second level; and third bondpads adapted to couple to a light-emitting diode (LED), the third bondpads at a third level. The third bondpads coupled to fourth bondpads at the base of the interposer at the second level; and the second and fourth bondpads couple to conductors of a cable with the first, second, and third level different. An endoscope optical includes the cavity interposer an LED, and a chip-type camera cube electrically bonded to the first bondpads; the LED is bonded to the third bondpads; and a top of the chip-type camera cube and a top of the LED are at a same level.Type: GrantFiled: May 18, 2022Date of Patent: March 18, 2025Assignee: OmniVision Technologies, Inc.Inventors: Teng-Sheng Chen, Wei-Ping Chen, Wei-Feng Lin, Jau-Jan Deng
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Publication number: 20250082033Abstract: Disclosed are an electronic atomizer and a liquid supply method therefor. The liquid supply method includes: obtaining an atomization parameter of an atomizing unit after the atomizing unit is connected to a circuit; calculating a real-time power of the atomizing unit according to the atomization parameter; determining an operating time ratio of an air supply unit to the atomizing unit according to the real-time power; determining a duty cycle of the air supply unit according to the operating time ratio, and controlling the air supply unit to supply air to a liquid storage unit according to the duty cycle. The electronic atomizer supplies liquid using the liquid supply method. The invention solves the problem that it is difficult to keep a balance between atomizing liquid consumption and atomizing liquid supply of the atomizing unit.Type: ApplicationFiled: April 29, 2022Publication date: March 13, 2025Applicant: SHENZHEN HUACHENGDA PRECISION INDUSTRY CO. LTD.Inventor: Ping CHEN
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Publication number: 20250085433Abstract: Disclosed are methods, apparatuses, and systems. A method can include receiving, by one or more processors, navigation data from a navigation system. The method can include receiving first correction data from a first correction source and receiving second correction data from a second correction source. The method can include determining first positional data based on the navigation data and the first correction data and second positional data based on the navigation data and the second correction data. The method can include determining a first accuracy value associated with the first positional data and a second accuracy value associated with the second positional data. The method can include selecting one of the first navigation system and the second navigation system for positional tracking based, in part, on at least one of the first accuracy value and the second accuracy value.Type: ApplicationFiled: September 11, 2024Publication date: March 13, 2025Applicant: Hemisphere GNSS, Inc.Inventors: Jian Ping Chen, Benjamin Brownlee, Viet Duong, Alim Kanji, Michael Whitehead
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Patent number: 12250833Abstract: A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.Type: GrantFiled: December 27, 2021Date of Patent: March 11, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Yu-Ping Chen, Chun-Shun Huang
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Patent number: 12249988Abstract: An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.Type: GrantFiled: June 21, 2021Date of Patent: March 11, 2025Assignee: Altera CorporationInventors: Ping-Chen Liu, Guang Chen, Venu Kondapalli