Patents by Inventor Ping Chen

Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250174492
    Abstract: An interconnection structure includes a semiconductor substrate, an interlayer dielectric layer that is disposed over the semiconductor substrate, and a metal trench that is formed in the interlayer dielectric layer. The interlayer dielectric layer is formed with an air gap, and the metal trench is disposed over the air gap.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 29, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Yun KU, Chia-Chen LEE, Wei-Chen CHU, Chia-Tien WU, Hsin-Ping CHEN
  • Publication number: 20250176251
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: January 27, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 12311498
    Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.
    Type: Grant
    Filed: February 9, 2024
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng
  • Patent number: 12312332
    Abstract: The present invention is directed to heteroaryl pyrrolidine and piperidine compounds which are agonists of orexin receptors. The present invention is also directed to uses of the compounds described herein in the potential treatment or prevention of neurological and psychiatric disorders and diseases in which orexin receptors are involved. The present invention is also directed to compositions comprising these compounds. The present invention is also directed to uses of these compositions in the potential prevention or treatment of such diseases in which orexin receptors are involved.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 27, 2025
    Assignee: Merck Sharp & Dohme LLC
    Inventors: Stephane L. Bogen, Ping Chen, Dane James Clausen, Jinsong Hao, Dipannita Kalyani, Michael T. Rudd, Shawn P. Walsh, Lan Wei, Dexi Yang
  • Publication number: 20250150503
    Abstract: Described are techniques for a control plane. The techniques include receiving, at the control plane hosted on a service-provider data center, a request to perform a computing resource operation at a remote data center, where the control plane is used to manage computing resources located at the remote data center. The techniques further include creating a data object at the service-provider data center to represent a status of the computing resource operation, and updating the data object in response to receiving indications of events associated with performance of the computing resource operation at the remote data center. The techniques further include receiving, at the control plane, a status request for the computing resource operation, querying the data object maintained at the service-provider data center for the status of the computing resource operation, and providing the status of the computing resource operation represented by the data object.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Joseph W. Cropper, Julio Oliva, Ping Chen, Daniel Nhiem Nguyen, Corradino D. Jones, Hariganesh Muralidharan, John B. Carter, Shayma Venugopal, Paul Bernell Finley, JR.
  • Patent number: 12294023
    Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Ping Chen, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20250140683
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a via, an air gap, an etching stop layer, a second dielectric layer, and a second metal layer. The first metal layer is embedded in the first dielectric layer. The first metal layer includes a first conductive line and a second conductive line. The via is disposed on the first conductive line. The air gap is located on the second conductive line. The sustaining layer covers the air gap. The etching stop layer is disposed on the sustaining layer. The second dielectric layer is disposed on the etching stop layer. The second metal layer is disposed on the second dielectric layer and connected to the via.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Pu CHOU, Chia-Tien WU, Hsin-Ping CHEN, Wei-Chen CHU
  • Publication number: 20250140697
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of conductive interconnects arranged within a dielectric structure having a plurality of inter-level dielectric (ILD) layers stacked onto one another. A heat pipe vertically extends through the plurality of ILD layers. A high thermal conductivity layer is sandwiched between neighboring ones of the plurality of ILD layers. The high thermal conductivity layer laterally extends from over one or more of the plurality of conductive interconnects to the heat pipe.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 1, 2025
    Inventors: Ming-Hsien Lin, Kun-Yen Liao, Hsin-Ping Chen, Chia-Tien Wu, Hsiao-Kang Chang
  • Patent number: 12288812
    Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chen-Ping Chen, Chih-Chung Chiu, Ke-Chia Tseng, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
  • Publication number: 20250130455
    Abstract: A display apparatus (2) and an electronic device (0). The display apparatus (2) comprises a first functional layer (211) of a touch screen (21), a touch sensing layer (212) of the touch screen (21), a second functional layer (223) of a display screen (22), a liquid crystal panel (221) of the display screen (22), a third functional layer (224) of the display screen (22), and a backlight module (222) of the display screen (22), which are arranged in a stacked manner, wherein the touch screen (21) is bonded with the display screen (22), and at least two of the first functional layer (211), the touch sensing layer (212), an adhesive (23), the second functional layer (223) and the third functional layer (224) are provided with an anti-glare structure and/or a blue light blocking structure.
    Type: Application
    Filed: November 11, 2022
    Publication date: April 24, 2025
    Applicant: HUIZHOU TCL MOBILE COMMUNICATION CO., LTD.
    Inventors: Ping CHEN, Zhuwei QIU, Ke LIN, Yang YU, Jitao MA
  • Patent number: 12280414
    Abstract: A stamping assembly includes an upper die, a lower die, first pins and second pins. Each of the upper and lower dies has columns of depressions and columns of guiding holes. Each column of the guiding holes is disposed between two adjacent columns of the depressions. The depressions of one of the upper and lower dies are registered with the guiding holes of another one of the upper and lower dies. The first pins and second pins are respectively positioned in the guiding holes of the upper and lower dies and extend outwardly. The first pins and the second pins are respectively arranged into first and second matrices.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 22, 2025
    Assignees: NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY, CERAM ENERGY TECHNOLOGY CO., LTD.
    Inventors: Sea-Fue Wang, Fan-Ping Chen, Hsi-Chuan Lu
  • Publication number: 20250125251
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Su, Chia-Wei Su, Tsu-Chun Kuo, Wei-Hao Liao, Hsin-Ping Chen, Yung-Hsu Wu, Ming-Han Lee, Shin-Yi Yang, Chih Wei LU, Hsi-Wen Tien, Meng-Pei Lu
  • Publication number: 20250126828
    Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. The gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. The source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. The first doped region is disposed in the substrate and adjacent to the source region. The second doped region is disposed in the substrate and located under the first doped region. The conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 17, 2025
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Ping Chen, Chen-Lun Ting
  • Publication number: 20250125189
    Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Hwei-Jay CHU, Yu-Teng DAI, Hsin-Chieh YAO, Yung-Hsu WU, Li-Ling SU, Chia-Wei SU, Hsin-Ping CHEN
  • Patent number: 12274755
    Abstract: The present disclosure relates to a field of hollow silica nanospheres. Particularly, the present disclosure relates to silica nanoparticles as adjuvant to induce or enhance immune response or as carrier to deliver antigen to a body.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 15, 2025
    Assignee: NANO TARGETING & THERAPY BIOPHARMA INC.
    Inventors: Chung-Yuan Mou, Cheng-Hsun Wu, Si-Han Wu, Yi-Ping Chen
  • Publication number: 20250120167
    Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
  • Publication number: 20250118594
    Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei SU, Hsin-Ping CHEN, Yung-Hsu WU, Li-Ling SU, Chan-Yu LIAO, Shao-Kuan LEE, Ting-Ya LO, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Publication number: 20250120151
    Abstract: A method of fabricating a semiconductor structure includes forming a recess in an active channel structure by removing a portion thereof, filling the recess with a dielectric material, forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material, and forming a gate structure comprising a first gate structure and a second gate structure around the active channel structure. A width of the dielectric material in the recess is greater than a width of the first gate structure and a width of the second gate structure.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: KUEI-YU KAO, Shih-Yao LIN, Chen-Ping Chen, Chih-Han Lin, MING-CHING CHANG, CHAO-CHENG CHEN
  • Publication number: 20250120087
    Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.
    Type: Application
    Filed: November 6, 2023
    Publication date: April 10, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Jen Yang Hsueh, Chien-Hung Chen, Tzu-Ping Chen, Chia-Hui Huang, Chia-Wen Wang, Chih-Yang Hsu, Ling Hsiu Chou
  • Patent number: D1072322
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: April 22, 2025
    Inventor: Ping Chen