Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract: The present invention proposes a liquid crystal alignment device and the liquid crystal alignment device comprises light sources, a light emitting plate and reflective plates, and the light sources are disposed on the light emitting plate; the reflective plate is disposed on a side surface of the light sources, and a reflective surface of each of the reflective plates is facing the light sources; the reflective surface of the reflective plate appears to be a rough shape. Therefore, even if the UV rays emitted by the light source are not uniform, the evenness of the UV rays transmitted to the liquid crystal layer can be ensured after the reflection of the reflective plate, and thereby avoid the Mura occurring during the alignment process. The product yield is increased and the display result of the LCD is guaranteed.

Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.

Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: A polysaccharide-protein binding model of SBD, and a fibril-forming 14-residue peptide consisting of X1NNNX2X3NYQX4X5X6X7X8, wherein the X1 and X8 mean a pair of opposite charged amino acid residues, and the X2, X3, X4, X5, X6, or X7 means an amino acid residue is described. A mixture for diminishing a polysaccharide, comprising at least two starch binding domains (SBDs) and a polysaccharide in a helix form is also presented. A method of providing an oligosaccharide, and a method of producing an amyloid-like fibril and use thereof are further described.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure.

Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.

Abstract: A data capture device including a signal processing unit, a frequency locked circuit and a match circuit is provided. The signal processing unit converts a radio frequency signal to a return-to-zero signal. The frequency locked circuit estimates a minimum interval length by the return-to-zero signal in a plurality of detecting periods, and generates an enable signal according to the minimum interval length and the return-to-zero signal. The frequency locked circuit determines whether to calibrate the enable signal according to a distribution of a plurality of enable pulses in the enable signal to generate a sampling signal. The match circuit samples the return-to-zero signal by the sampling signal and generates a synchronization signal according to a sampling result. The match circuit generates a composite synchronization signal by a virtual signal and the synchronization signal, and captures a plurality of row data from the return-to-zero signal according to the composite synchronization signal.

Abstract: A mechanism modulates a fluid flow in a diffuser flow path of a compressor diffuser, including: a shroud disposed on the diffuser flow path and having a cam and a driving wheel fixed base; a diffuser vane having a diffuser guide vane disposed in the diffuser flow path and a diffuser vane shaft fixedly disposed on the diffuser vane that penetrates from the diffuser flow path through the shroud; a driving ring sleeved on the cam and having a moving bar; a sliding block having one end connected with one end the diffuser vane shaft that penetrates through the shroud, and the other end sleeved on a sliding groove formed on the moving bar; a driving wheel disposed in the driving wheel fixed base and having a driving shaft connected to an actuator outside of the compressor; and a driving cable connected to the driving wheel and the driving ring.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.

Abstract: A method of forming a pattern in a substrate is provided, in which the substrate having a pattern region is provided first. A plurality of stripe-shaped mask layers is formed on the substrate in the pattern region. Each of at least two adjacent stripe-shaped mask layers among the stripe-shaped mask layers has a protrusion portion and the protrusion portions face to each other. A spacer is formed on sidewalls of the stripe-shaped mask layers, wherein a thickness of the spacer is greater than a half of a distance between two of the protrusion portions. Subsequently, the stripe-shaped mask layers are removed. An etching process is performed by using the spacer as a mask to form trenches in the substrate. Thereafter, the trenches are filled with a material.

Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.

Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE? is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.

Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE? is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.