Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: An automated security infrastructure is disclosed that includes security agents that are designed to analyze security issues. The security agents process events received from event-messages, and records data associated with a security issue in a ticket. Security and management personnel are kept informed based on notification subscription lists. Assigned security personnel's progress in resolving outstanding security issues is monitored until those issues are resolved.

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: The present invention provides a method for identifying starch binding sites of starch binding domain in CBM family. The CBM family is consisting of CBM20, CBM21, CBM25, CBM26, CBM34, and CBM41. The method further comprises predicting starch binding sites of starch binding domain in CBM family using the identified starch binding sites of starch binding domain with same topology.

Abstract: Disclosed are a test piece and the manufacturing method thereof The test piece includes an insulating substrate and a circuit pattern structure formed on the insulating substrate, wherein circuit pattern structure includes a first metal pattern layer, a second metal pattern layer, a third metal pattern layer, a fourth metal pattern layer, and a fifth metal pattern layer. The first metal pattern layer, the second metal pattern layer, the third metal pattern layer, the fourth metal pattern layer, and the fifth metal pattern layer have same pattern shapes and positions thereof are overlapping in a plane. The first metal pattern layer and the second metal pattern layer are nano-metal films formed by vacuum coating, therefore, the test piece has excellent uniformity of film and low resistance to provide a stable test current to prevent the judging mistakes and to improve the test efficiency.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.

Abstract: A data capture device including a signal processing unit, a frequency locked circuit and a match circuit is provided. The signal processing unit converts a radio frequency signal to a return-to-zero signal. The frequency locked circuit estimates a minimum interval length by the return-to-zero signal in a plurality of detecting periods, and generates an enable signal according to the minimum interval length and the return-to-zero signal. The frequency locked circuit determines whether to calibrate the enable signal according to a distribution of a plurality of enable pulses in the enable signal to generate a sampling signal. The match circuit samples the return-to-zero signal by the sampling signal and generates a synchronization signal according to a sampling result. The match circuit generates a composite synchronization signal by a virtual signal and the synchronization signal, and captures a plurality of row data from the return-to-zero signal according to the composite synchronization signal.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.

Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.

Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.

Abstract: A photovoltaic organic light emitting diodes (PV-OLED) device and manufacturing method thereof are introduced. The PV-OLED device includes a substrate, a solar cell module, and a plurality of organic light emitting diodes. The solar cell module is disposed on a surface of the substrate. The organic light emitting diodes are disposed on the same surface of the substrate that the solar cell module is disposed on. The organic light emitting diode is electrically isolated from the solar cell module. The solar cell module can apply power to the organic light emitting diodes for emitting light.

Abstract: The present invention provides a method for identifying starch binding sites of starch binding domain in CBM family. The CBM family is consisting of CBM20, CBM21, CBM25, CBM26, CBM34, and CBM41. The method further comprises predicting starch binding sites of starch binding domain in CBM family using the identified starch binding sites of starch binding domain with same topology.

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract: A mechanism modulates a fluid flow in a diffuser flow path of a compressor diffuser, including: a shroud disposed on the diffuser flow path and having a cam and a driving wheel fixed base; a diffuser vane having a diffuser guide vane disposed in the diffuser flow path and a diffuser vane shaft fixedly disposed on the diffuser vane that penetrates from the diffuser flow path through the shroud; a driving ring sleeved on the cam and having a moving bar; a sliding block having one end connected with one end the diffuser vane shaft that penetrates through the shroud, and the other end sleeved on a sliding groove formed on the moving bar; a driving wheel disposed in the driving wheel fixed base and having a driving shaft connected to an actuator outside of the compressor; and a driving cable connected to the driving wheel and the driving ring.

Abstract: A system and method for monitoring and controlling oil return to a compressor, characterized by monitoring and controlling oil level, oil temperature, and compressor outlet pressure, so as to determine whether the oil level is lower than a predetermined level threshold, whether the temperature in the lubricating oil box is lower than a predetermined temperature threshold, and whether the compressor outlet pressure exceeds a predetermined pressure threshold, so as to control the flow of lubricating oil returned to the oil box by controlling the valve opening of the oil return valve according to a non-segmentation principle or a segmentation principle, ensure sufficient lubricating oil in the oil box, and enhance efficiency of the system.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.