Patents by Inventor Ping Han

Ping Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • WAFER BASED CORROSION & TIME DEPENDENT CHEMICAL EFFECTS
    Publication number: 20200118896
    Abstract: Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Leonard Tedeschi, Benjamin Schwarz, Changhun Lee, Ping Han Hsieh, Adauto Diaz, JR., Daniel T. McCormick
  • ARGMAX FUNCTION ANALOG CIRCUIT
    Publication number: 20200110579
    Abstract: An argmax circuit includes input nodes coupled to a first set of comparators to receive a plurality of analog input signals each associated with a channel number, the first set of comparators outputting a plurality of first analog results and input nodes coupled to a second set of comparators to receive and process the plurality of first analog results, the second set of comparators outputting a plurality of second analog results processed by additional comparators in a cascading manner in a forward direction until a single comparator remains with a single output. A plurality of comparators including the first set, the second set, and the additional comparators are executed in a reverse direction to determine the channel number from which the single output originated from.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Xin Zhang, Dennis M. Newns, Xiaodong Cui, Jin Ping Han
  • BEOL CROSS-BAR ARRAY FERROELECTRIC SYNAPSE UNITS FOR DOMAIN WALL MOVEMENT
    Publication number: 20200066755
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • INDIRECT READOUT FET
    Publication number: 20200058641
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • IMAGE SENSOR WITH ANALOG SAMPLE AND HOLD CIRCUIT CONTROL FOR ANALOG NEURAL NETWORKS
    Publication number: 20200053299
    Abstract: According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.
    Type: Application
    Filed: August 10, 2018
    Publication date: February 13, 2020
    Inventors: Xin Zhang, Jin Ping Han, Dennis M. Newns, Xiaodong Cui
  • Indirect readout FET
    Patent number: 10559562
    Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jin-Ping Han, Yulong Li, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • ANTI-ELECTROMAGNETIC INTERFERENCE CIRCUIT BOARD
    Publication number: 20200015350
    Abstract: An anti-electromagnetic interference circuit board includes a circuit board and a magnetic conductor. The circuit board has a plurality of vias, and the magnetic conductor is covered on the circuit board to cover some of the vias. The magnetic conductor includes a plate, a carrier, a sprayed magnetic conductor, and a wave absorbing magnetic conductor.
    Type: Application
    Filed: June 18, 2019
    Publication date: January 9, 2020
    Inventors: Ping-Han TSOU, Li-Chien WAN
  • SYMMETRICALLY PROGRAMMABLE RESISTIVE SYNAPSE FOR RPU USING CURRENT-PROGRAMMED SINGLE DOMAIN WALL FERROELECTRIC
    Publication number: 20200005848
    Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Martin M. Frank, Jin-Ping Han, Dennis M. Newns, Paul M. Solomon, Xiao Sun
  • MULTI-TERMINAL CROSS-POINT SYNAPTIC DEVICE USING NANOCRYSTAL DOT STRUCTURES
    Publication number: 20200005129
    Abstract: Described herein is a crossbar array that includes a cross-point synaptic device at each of a plurality of crosspoints. The cross-point synaptic device includes a weight storage element comprising a set of nanocrystal dots. Further, the cross-point synaptic device includes at least three terminals for interacting with the weight storage element, wherein a weight is stored in the weight storage element by sending a first electric pulse via a gate terminal from the at least three terminals, the first electric pulse causes the nanocrystal dots to store a corresponding charge, and the weight is erased from the weight storage element by sending a second electric pulse via the gate terminal, the second electric pulse having an opposite polarity of the first electric pulse.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Kevin K. Chan, Martin M. Frank, JIN PING HAN
  • Wafer based corrosion and time dependent chemical effects
    Patent number: 10515862
    Abstract: Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 24, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Leonard Tedeschi, Benjamin Schwarz, Changhun Lee, Ping Han Hsieh, Adauto Diaz, Daniel T. McCormick
  • CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME
    Publication number: 20190378555
    Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 12, 2019
    Inventors: Jin Ping Han, Xiao Sun, Teng Yang
  • BEOL cross-bar array ferroelectric synapse units for domain wall movement
    Patent number: 10468432
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • SUPERKINE
    Publication number: 20190330309
    Abstract: Contemplated compositions and methods comprise chimeric molecule complexes that advantageously provide activating signaling to immune competent cells when bound to ALL cells. Furthermore, chimeric molecule complexes include an Fc portion to extend serum half live time and facilitate purification.
    Type: Application
    Filed: June 14, 2019
    Publication date: October 31, 2019
    Inventors: Patrick Soon-Shiong, Hing C. Wong, Peter Rhode, Bai Liu, Xiaoyun Zhu, Kai-Ping Han
  • Artificial Synapse with Hafnium Oxide-Based Ferroelectric Layer in CMOS Back-End
    Publication number: 20190326387
    Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • IL-15 variants and uses thereof
    Patent number: 10450359
    Abstract: The instant invention provides soluble fusion protein complexes and IL-15 variants that have therapeutic and diagnostic use, and methods for making the such proteins. The instant invention additionally provides methods of stimulating or suppressing immune responses in a mammal using the fusion protein complexes and IL-15 variants of the invention.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 22, 2019
    Assignee: Altor Bioscience Corporation
    Inventors: Hing C. Wong, Peter Rhode, Xiaoyun Zhu, Kai-ping Han
  • METHOD OF IMAGE FUSION ON CAMERA DEVICE EQUIPPED WITH MULTIPLE CAMERAS
    Publication number: 20190297275
    Abstract: A camera device is provided. The camera device includes: a first imaging section, a second imaging section, a third imaging section, and a processor. The first imaging section, second imaging section, and third imaging section capture a first image, a second image, and a third image of a scene with a first field of view (FOV), a second FOV1 and a third FOV. The processor is configured to generate a first output image by performing a first image-fusion process on the first image, the second image, and a third image in response to a zooming factor of the camera device being between a first zooming factor and a second zooming factor, wherein the first FOV is wider than the second FOV, and the second FOV is wider than the third FOV, and the second zooming factor is greater than the first zooming factor.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 26, 2019
    Inventors: Ping-Han LEE, Te-Hao CHANG
  • One-transistor synapse cell with weight adjustment
    Patent number: 10395713
    Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Xiao Sun, Teng Yang
  • Artificial Synapse with Hafnium Oxide-Based Ferroelectric Layer in CMOS Front-End
    Publication number: 20190252499
    Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Artificial Synapse with Hafnium Oxide-Based Ferroelectric Layer in CMOS Front-End
    Publication number: 20190252500
    Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan
  • Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS back-end
    Patent number: 10381431
    Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Takashi Ando, Xiao Sun, Jin Ping Han, Vijay Narayanan