Patents by Inventor Ping Kang

Ping Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153861
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.
    Type: Application
    Filed: January 14, 2024
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11927937
    Abstract: Disclosed is a prediction method for tool remaining life of a numerical control machine tool based on a hybrid neural model, including: constructing a hybrid neural network model, specifically including the following steps: constructing sample data according to the sampling frequency of tool data; obtaining a first feature vector representing the tool life by utilizing a convolutional neural network and a long short-term memory network; generating working condition signals of sampling points into a second feature vector representing the tool life by utilizing an NFM neural network; and inputting a current working time of a tool and the acquired feature vectors into a multi-layer perceptron for fusion to predict the tool life.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF INDUSTRIAL INTERNET, CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Qingqing Huang, Yan Han, Zhen Kang, Yan Zhang, Ping Wang
  • Patent number: 11916009
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.
    Type: Grant
    Filed: May 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Huang, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Patent number: 11866450
    Abstract: Compounds of Formula (I): pharmaceutically acceptable salts thereof, deuterated derivatives of any of the foregoing, and metabolites of any of the foregoing are disclosed. Pharmaceutical compositions comprising the same, methods of treating cystic fibrosis using the same, and methods for making the same are also disclosed.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 9, 2024
    Assignee: Vertex Pharmaceuticals Incorporated
    Inventors: Jeremy J. Clemens, Alexander Russell Abela, Corey Don Anderson, Brett B. Busch, Weichao George Chen, Thomas Cleveland, Timothy Richard Coon, Bryan Frieman, Senait G. Ghirmai, Peter Grootenhuis, Anton V. Gulevich, Sara Sabina Hadida Ruah, Clara Kuang-Ju Hsia, Ping Kang, Haripada Khatuya, Jason McCartney, Mark Thomas Miller, Prasuna Paraselli, Fabrice Pierre, Sara E. Swift, Andreas Termin, Johnny Uy, Carl V. Vogel, Jinglan Zhou
  • Publication number: 20230357191
    Abstract: Compounds of Formula (I): pharmaceutically acceptable salts thereof, deuterated derivatives of any of the foregoing, and metabolites of any of the foregoing are disclosed. Pharmaceutical compositions comprising the same, methods of treating cystic fibrosis using the same, and methods for making the same are also disclosed. Also disclosed are solid state forms of Compound 1 and salts and solvates thereof.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 9, 2023
    Inventors: Alexander Russell Abela, Timothy Alcacio, Corey Anderson, Paul Timothy Angell, Minson Baek, Jeremy J. Clemens, Thomas Cleveland, Lori Ann Ferris, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Anton V. Gulevich, Sara Sabina Hadida Ruah, Clara Kuang-Ju Hsia, Robert M. Hughes, Pramod Virupax Joshi, Ping Kang, Ali Keshavarz-Shokri, Haripada Khatuya, Paul John Krenitsky, Jason McCartney, Mark Thomas Miller, Prasuna Paraselli, Fabrice Jean Denis Pierre, Yi Shi, Muna Shrestha, David Andrew Siesel, Kathy Stavropoulos, Andreas P. Termin, Fredrick F. Van Goor, Johnny Uy, Timothy John Young, Jinglan Zhou
  • Patent number: 11810793
    Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20230335502
    Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
  • Publication number: 20230326826
    Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11728278
    Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu
  • Patent number: 11728254
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11715675
    Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Ping-Kang Huang, Sao-Ling Chiu, Tsung-Yu Chen, Tsung-Shu Lin, Chien-Yuan Huang, Chen-Hsiang Lao
  • Patent number: 11555090
    Abstract: The present invention relates to a thermoplastic polyurethane fiber and a method for producing the same. A thermoplastic polyurethane material is firstly provided and subjected to a molten extruding process to form a fiber material. Next, an extension process is performed to the fiber material to obtain the thermoplastic polyurethane fiber of the present invention. The thermoplastic polyurethane fiber has a lower thermal shrinking property, thereby meeting requirements of the application.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 17, 2023
    Assignee: SAN FANG CHEMICAL INDUSTRY CO., LTD.
    Inventors: Chih-Yi Lin, Kuo-Kuang Cheng, Kao-Lung Yang, Po-Ping Kang
  • Patent number: 11552054
    Abstract: A package structure includes a semiconductor device, a circuit substrate and a heat dissipating lid. The semiconductor device includes a semiconductor die. The circuit substrate is bonded to and electrically coupled to the semiconductor device. The heat dissipating lid is bonded to the circuit substrate and thermally coupled to the semiconductor device, where the semiconductor device is located in a space confined by the heat dissipating lid and the circuit substrate. The heat dissipating lid includes a cover portion and a flange portion bonded to a periphery of the cover portion. The cover portion has a first surface and a second surface opposite to the first surface, where the cover portion includes a recess therein, the recess has an opening at the second surface, and a thickness of the recess is less than a thickness of the cover portion, where the recess is part of the space.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Lin, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Patent number: 11545438
    Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
  • Publication number: 20220367208
    Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20220359355
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11495472
    Abstract: One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 ?m thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Yu Lu, Ping-Kang Huang, Sao-Ling Chiu, Shang-Yun Hou
  • Publication number: 20220336362
    Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
  • Publication number: 20220314800
    Abstract: A vehicle multimedia system includes one or more displays configured to output information at a vehicle, and a processor in communication with the one or more displays. The processor is programmed to access a user's social networking website, communicate post information associated with the user's social networking website, utilize a filter associated with the post information, wherein the filter is configured to ignore post information in response to one or more settings associated with the filter, and output filtered post information at the one or more displays at the vehicle, wherein the post information includes at least text associated with the post information and user information associated with the post information.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Inventors: Yu ZHANG, Brittany SCHOENOW, Bilal ALASRY, Doua VANG, Vikas UPMANUE, Te-Ping KANG