Patents by Inventor Ping Lu

Ping Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12630876
    Abstract: The present invention provides a mass spectrometry-based method and a kit for genotyping of platelet and neutrophil antigens and glycoproteins, which are used for genotyping of platelet-specific antigens, platelet CD36 glycoproteins and neutrophil antigens; by designing an optimal primer combination, problems such as homologous sequences and rich GC are overcome, moreover, by improving amplification reaction conditions and using nucleic acid mass spectrometry as a platform, 35 platelet-specific antigen polymorphic sites, 10 CD36 polymorphic sites and 8 neutrophil antigen polymorphic sites can be simultaneously detected in 2 reactions. The present invention has the characteristics of high specificity and sensitivity, and fast and high throughput, and can be used in clinic, scientific research, platelet donor routine screening, etc.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: May 19, 2026
    Assignee: SHANGHAI BLOOD CENTER
    Inventors: Luyi Ye, Huijun Zhu, Ruishu Li, Min Fu, Ping Lu, Ziyan Zhu
  • Patent number: 12620625
    Abstract: The present disclosure relates to an electrolyte solution for a lithium-ion battery. The electrolyte solution includes an organic solvent, a lithium salt, and an additive. The electrolyte solution provided in the present disclosure includes a 6-membered heterocyclyl carboxylic anhydride additive, and can effectively inhibit gas production and the increase of interface impedance in the battery, improve the high-temperature stability of the battery, and prolong the service life of the battery.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: May 5, 2026
    Assignee: BYD COMPANY LIMITED
    Inventors: Feiyan Qiao, Ping Lu, Haijun Wang, Rong Hao, Yi Pan
  • Publication number: 20260118864
    Abstract: The present invention discloses a full cycle distributed monitoring and early warning method for a foundation pit structure, comprising: after the construction of a foundation pit is completed, building a distributed data sensor network of the foundation pit structure to collect real-time data of the foundation pit structure; installing sensor communication modules at all sensor installation points in the data sensor network of the foundation pit structure, and establishing a sensor communication transmission mechanism; analyzing and processing the real-time data of the foundation pit structure by an integrated computing service unit to obtain classification monitoring and overall monitoring results of the foundation pit structure, and issuing corresponding early warning information.
    Type: Application
    Filed: January 3, 2025
    Publication date: April 30, 2026
    Inventors: BIN HE, GANG LI, MENG ZHANG, PING LU
  • Patent number: 12613372
    Abstract: A method and apparatus for inscribing a high-temperature stable Bragg grating in an optical waveguide, comprising the steps of: providing the optical waveguide; providing electromagnetic radiation from an ultrashort pulse duration laser, wherein the wavelength of the electromagnetic radiation has a characteristic wavelength in the wavelength range from 150 nanometers (nm) to 2.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: April 28, 2026
    Assignee: NATIONAL RESEARCH COUNCIL OF CANADA
    Inventors: Cyril Hnatovsky, Nurmemet Abdukerim, Dan Grobnic, Robert Walker, Stephen Mihailov, Ping Lu, Huimin Ding, David Coulas, Kasthuri De Silva
  • Patent number: 12609707
    Abstract: Interfaces between clock domains of an integrated circuit (IC) depend on synchronization of phase-locked loops (PLLs) that generate clocks in the different domains and on how each PLL responds to jitter in a shared reference clock. The well-controlled same bandwidth (and loop dynamic) for those PLLs renders the same and, therefore, ignorable reference jitter contribution. As a key component that determines a digital PLL bandwidth, digitally controlled oscillator (DCO) may have its gain vary with process, temperature, and supply IR drop from chip to chip or even module to module. A calibration circuit provides a gain correction factor to achieve a nominal gain in DCO as well as a desired/target PLL loop bandwidth. In some examples, the calibration circuit in each PLL determines a gain correction factor that causes the PLLs to have a common jitter response and stores the gain correction factors in the calibration circuits.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: April 21, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ping Lu, Bupesh Pandita, Minhan Chen
  • Patent number: 12592687
    Abstract: To compensate for the non-linearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the non-linearities of the interpolated clocks have opposite polarities, they may have different magnitudes causing some non-linearity. A weighted summing PI that sums interpolated clocks of two PI circuits includes a weighted summing circuit that employs a weight signal to generate a weighted summed interpolated clock having an interpolated phase, based on the weight signal, between the phases of the interpolated clocks. As a result, the phase of the weighted summed interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than the other. A weight calibration circuit may be included to select a balanced weight signal to reduce non-linearity in the weighted summing PI.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: March 31, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ping Lu, Minhan Chen
  • Publication number: 20260003386
    Abstract: Systems and methods are disclosed for reduced-power serial data links. A clock-forwarded serial link carries a clock lane and one or more data lanes. Every active serial data cycle is accompanied by its own serial clock edge: a clock delay allows the same clock edge to drive data at a transmitter and latch data at a receiver. Power is saved by idling the serial clock when data is not being transmitted. A valid signal can be omitted, providing a space saving. At the destination, similar clock-forwarding and delay enables a single parallel clock edge to drive data to the boundary of its clock domain, e.g. from a deserializer to a FIFO. The data link exhibits zero-cycle entry and exit. Variations with half- or single-cycle entry or exit are disclosed.
    Type: Application
    Filed: June 26, 2024
    Publication date: January 1, 2026
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Charles Walter BOECKER, Jin LIANG, Michael Raymond TROMBLEY, Eric Douglas GROEN, Ping LU, Simon S. LI, Shankar Srinivasa TANGIRALA, Roxanne VU, Ravi SHIVNARAINE
  • Publication number: 20250378039
    Abstract: Multi-die systems with modular die-to-die link macros for enabling die-to-die communication are described. A multi-die system includes a first die comprising a first set of modular die-to-die (D2D) transmit link macros and a first set of modular D2D receive link macros. The multi-die system further includes a second die, coupled to the first die via die-to-die (D2D) links, comprising a second set of modular D2D transmit link macros and a second set of modular D2D receive link macros. Each of the transmit/receive macros has the same physical shape, size, and the bandwidth capacity. The modularity associated with respective modular D2D transmit link macros and respective modular D2D receive link macros allows different combinations of an amount of bandwidth for data being transmitted or received via the D2D links and different amounts of edge depths for the first die and the second die along the die edge.
    Type: Application
    Filed: June 11, 2024
    Publication date: December 11, 2025
    Inventors: Charles Walter BOECKER, Jin LIANG, Michael Raymond TROMBLEY, Jonathan HOLLAND, Eric Douglas GROEN, Ping LU, Simon Shichi LI, Shankar Srinivasa TANGIRALA, Shaishav A. DESAI, Roxanne VU, Ravi SHIVNARAINE
  • Patent number: 12468309
    Abstract: The embodiment of this present disclosure provides a control method of unmanned aerial vehicle (UAV) hovering in tunnel, which comprises the following steps: acquiring hovering information of hovering position of UAV; acquiring the position information of the current position of the UAV; determining flight parameters based on hovering information and position information. The flight parameters are used to control the UAV to move from the current position to the hovering position.
    Type: Grant
    Filed: April 2, 2022
    Date of Patent: November 11, 2025
    Assignee: TONGJI UNIVERSITY
    Inventors: Bin He, Gang Li, Runjie Shen, Jie Chen, Zhipeng Wang, Ping Lu, Yimin Lou
  • Patent number: 12463649
    Abstract: In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: November 4, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ping Lu, Minhan Chen, Shaishav A. Desai
  • Publication number: 20250284050
    Abstract: A method and apparatus for inscribing a Bragg grating in the core of an optical waveguide. Electromagnetic radiation at a chosen wavelength passes through a diffractive optical element optimized for the wavelength such that a beam is generated on the waveguide having an interference pattern so as to form a Bragg grating in the core of the optical waveguide, the beam being sufficiently intense to cause a permanent (Type II) change in the index of refraction in the core in the form of at least one elongated micropore. The Bragg grating period can be selected to promote coupling of guided light into a radiation mode for detection by a detector to form a spectrometer. The Bragg grating is characterized by a scattering loss less than 10?5 dB per grating period at the Bragg resonance but outcoupling efficiency at visible wavelengths of 0.03% per grating period.
    Type: Application
    Filed: May 23, 2025
    Publication date: September 11, 2025
    Inventors: Abdullah RAHNAMA, Cyril HNATOVSKY, Rune LAUSTEN, Stephen MIHAILOV, Ping LU, Huimin DING, Robert WALKER, Kasthuri DE SILVA, Kasthuri
  • Patent number: 12404474
    Abstract: The invention is directed to environmentally stable solid lubricant coatings with bilayer transition-metal dichalcogenide structures that are designed to resist the effects of oxidation during long term storage, or during short exposures under conditions that would oxidize similar films that do not have these bilayer structures. In addition to improving oxidation resistance, these bilayer structures also facilitate the more rapid establishment of a low, steady-state friction coefficient than is possible with similar films that do not have these bilayer structures.
    Type: Grant
    Filed: July 9, 2024
    Date of Patent: September 2, 2025
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Michael T. Dugger, Steven Robert Larson, Alexander James Mings, John Francis Curry, Tomas Farley Babuska, Michael E. Chandross, Nathaniel S. Bobbitt, Ping Lu
  • Patent number: 12379695
    Abstract: Time-to-digital converters (TDC) employing a single-stage delay pair for a wide input range and reduced quantization noise in a phase-locked loop (PLL) and related fabrication methods are disclosed. Aspects disclosed in the detailed description include a single-stage Vernier time-to-digital converter (TDC) which mitigates the device mismatch impact and therefore avoids possible spurious tones in a fractional-N PLL application. Combined with a delta-sigma noise shaping stage and a ring-oscillator based coarse TDC, the invention achieves a good trade-off between resolution, detection range and PLL locking speed.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: August 5, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ping Lu, Minhan Chen
  • Publication number: 20250244238
    Abstract: One or more embodiments relates to a system for simultaneously detecting vibration and the presence of a target gas having a tunable fiber ring laser in electronic and optical communication with a vibration sensor and a gas detection sensor. One or more embodiments relate to a method for simultaneously measuring vibration and detecting the presence of a target gas in an environment having the steps of providing a system for simultaneously measuring vibration and detecting a target gas into an environment; sending an optical signal to a vibration sensor and gas detection sensor; and collecting and analyzing modified signals from the vibration sensor and gas detection sensor.
    Type: Application
    Filed: March 18, 2025
    Publication date: July 31, 2025
    Inventors: Nageswara Rao Lalam, Michael P. Buric, Ping Lu, Fei Lu, Tao Hong, Ruishu Feng Wright
  • Patent number: 12362902
    Abstract: A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.
    Type: Grant
    Filed: November 3, 2023
    Date of Patent: July 15, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ping Lu, Minhan Chen
  • Patent number: 12340152
    Abstract: A large-scale underground shield docking model test platform and a test method using the same are provided. The test platform includes a test soil tank, a partition wall, a shield docking model, and a freezing system. The test soil tank is of an underground foundation pit structure, the partition wall is disposed in the test soil tank to separate the test soil tank into a filling area and a non-filling area. The shield docking model is disposed in the filling area and is a reduced-scale test model. The shield docking model is provided with the freezing system, including a refrigeration system, a coolant circulation system, and freezing pipes. The freezing pipes are arranged on the shield docking model and are connected to the refrigeration system through the coolant circulation system. The refrigeration system is placed on a laminate in the non-filling area of the test soil tank.
    Type: Grant
    Filed: September 30, 2024
    Date of Patent: June 24, 2025
    Assignee: CCCC TUNNEL ENGINEERING CO., LTD.
    Inventors: Zhanhu Yao, Yazhou Zhang, Ping Lu, Yisheng Wang, Hui Li, Lei Zhang, Chi Wei, Xiao Yan, Yuqiang Liang, Yahui Li, Chao Zhang
  • Publication number: 20250200237
    Abstract: A large-scale underground shield docking model test platform and a test method using the same are provided. The test platform includes a test soil tank, a partition wall, a shield docking model, and a freezing system. The test soil tank is of an underground foundation pit structure, the partition wall is disposed in the test soil tank to separate the test soil tank into a filling area and a non-filling area. The shield docking model is disposed in the filling area and is a reduced-scale test model. The shield docking model is provided with the freezing system, including a refrigeration system, a coolant circulation system, and freezing pipes. The freezing pipes are arranged on the shield docking model and are connected to the refrigeration system through the coolant circulation system. The refrigeration system is placed on a laminate in the non-filling area of the test soil tank.
    Type: Application
    Filed: September 30, 2024
    Publication date: June 19, 2025
    Applicant: CCCC TUNNEL ENGINEERING CO., LTD.
    Inventors: Zhanhu YAO, Yazhou ZHANG, Ping LU, Yisheng WANG, Hui LI, Lei ZHANG, Chi WEI, Xiao YAN, Yuqiang LIANG, Yahui LI, Chao ZHANG
  • Patent number: 12313540
    Abstract: One or more embodiments relates to a system for simultaneously detecting vibration and the presence of a target gas having a tunable fiber ring laser in electronic and optical communication with a vibration sensor and a gas detection sensor. One or more embodiments relate to a method for simultaneously measuring vibration and detecting the presence of a target gas in an environment having the steps of providing a system for simultaneously measuring vibration and detecting a target gas into an environment; sending an optical signal to a vibration sensor and gas detection sensor; and collecting and analyzing modified signals from the vibration sensor and gas detection sensor.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: May 27, 2025
    Assignee: United States Department of Energy
    Inventors: Nageswara Rao Lalam, Michael P. Buric, Ping Lu, Fei Lu, Tao Hong, Ruishu Feng Wright
  • Publication number: 20250167776
    Abstract: To compensate for the non-linearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the non-linearities of the interpolated clocks have opposite polarities, they may have different magnitudes causing some non-linearity. A weighted summing PI that sums interpolated clocks of two PI circuits includes a weighted summing circuit that employs a weight signal to generate a weighted summed interpolated clock having an interpolated phase, based on the weight signal, between the phases of the interpolated clocks. As a result, the phase of the weighted summed interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than the other. A weight calibration circuit may be included to select a balanced weight signal to reduce non-linearity in the weighted summing PI.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 22, 2025
    Inventors: Ping LU, Minhan CHEN
  • Publication number: 20250150253
    Abstract: A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Ping LU, Minhan CHEN