Patents by Inventor Ping Lu
Ping Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973040Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.Type: GrantFiled: December 9, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Yang Hsieh, Chien-Chang Lee, Chia-Ping Lai, Wen-Chung Lu, Cheng-Kang Huang, Mei-Shih Kuo, Alice Huang
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Patent number: 11959829Abstract: A startup stage protection device used in Electric Multiple Unit (EMU) train coupler experiment is provided between two test cars. The startup stage protection device is arranged between and tightly abuts two test cars at the starting stage of the experiment to receive a compressing force in place of the coupler. The startup stage protection device separates from the two test cars after the end of the starting stage.Type: GrantFiled: May 30, 2019Date of Patent: April 16, 2024Assignee: CENTRAL SOUTH UNIVERSITYInventors: Ping Xu, Shuguang Yao, Bowen Tan, Yong Peng, Zhaijun Lu, Chengming Sun, Kai Xu, Qi Huang
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Patent number: 11963348Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.Type: GrantFiled: August 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
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Patent number: 11955370Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.Type: GrantFiled: September 18, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
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Patent number: 11953527Abstract: A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.Type: GrantFiled: August 24, 2022Date of Patent: April 9, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Ping Lu, Shaishav A. Desai, Minhan Chen
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Publication number: 20240110977Abstract: A comparator testing circuit and a testing method are provided. The comparator testing circuit includes a switching circuit, a comparator, and a determination circuit. The switching circuit receives a first signal, a second signal, and a switching signal, and outputs one of the first signal and the second signal as a first input signal and the other of the first signal and the second signal as a second input signal according to the switching signal. The comparator compares the first input signal with the second input signal to generate an output signal. The determination circuit determines whether the comparator is abnormal based on the switching signal and the output signal to generate an exception flag.Type: ApplicationFiled: September 25, 2023Publication date: April 4, 2024Applicant: Nuvoton Technology CorporationInventors: Chih-Ping Lu, Cheng-Chih Wang
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Publication number: 20240105723Abstract: A semiconductor substrate with an original semiconductor surface (OSS); a first gate region; a first concave formed in the semiconductor substrate and below the original semiconductor surface; a curved or depressed shape opening formed along the vertical direction of a sidewall of the semiconductor substrate in the first concave; and a first conductive region formed in the first concave and including a first doping region and a second doping region. Wherein the first doping region is formed based on the curved or depressed shape opening along the vertical direction of the sidewall of the semiconductor substrate.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun LU, Li-Ping HUANG
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Publication number: 20240107746Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes an access transistor defined within an active region of a semiconductor substrate and a storage capacitor disposed on the access transistor. A recessed gate structure of the access transistor extends into the active region from above the active region. Source/drain contacts of the access transistor are disposed on the active region at opposite sides of the recessed gate structure. The storage capacitor includes: a composite bottom electrode, formed by alternately stacked first conductive layers and second conductive layers, wherein each second conductive layer is sandwiched between a pair of the first conductive layers, and tunnels laterally extend through the second conductive layers, respectively; a capacitor dielectric layer, covering inner and outer surfaces of the composite bottom electrode; and a top electrode, in contact with the composite bottom electrode through the capacitor dielectric layer.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Publication number: 20240105846Abstract: A transistor structure and a formation method thereof are provided. The transistor structure includes a transistor device, formed on an active region of a semiconductor substrate, and including: a gate structure, disposed on the active region; gate spacers, formed along opposite sidewalls of the gate structure; source/drain structures, formed in recesses of the active region at opposite sides of the gate structure; and buried isolation structures, separately extending along bottom sides of the source/drain structures. Further, a channel portion of the active region between the source/drain structures is strained as a result of a strained etching stop layer lying above or dislocation stressors formed in the source/drain structures.Type: ApplicationFiled: September 22, 2023Publication date: March 28, 2024Applicant: Invention And Collaboration Laboratory Pte. Ltd.Inventors: Chao-Chun Lu, Li-Ping HUANG, Wen-Hsien Tu
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Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Patent number: 11943875Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.Type: GrantFiled: May 10, 2022Date of Patent: March 26, 2024Assignee: CHAMP TECH OPTICAL (FOSHAN) CORPORATIONInventors: Li-Ping Wang, Yung-Ping Lin, Yong-Kang Zhang, Qiu-Ri Zhang, You-Zhi Lu
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Publication number: 20240098219Abstract: Methods and systems are provided for a spatialized display of chat messages within a messaging platform. In an example method, a computing device displays a spatial chat user interface (UI) including a virtual background and one or more spatialized avatars overlaid on the virtual background. The computing device receives chat messages sent by a participant and displays, adjacent to the spatialized avatar representing the participant, chat bubbles having a first appearance. The computing device displays chat bubbles for other participants having a second appearance. The computing device receives one or more additional chat messages sent by the participant. The computing device displays additional chat bubbles corresponding to the additional chat messages having a third appearance and updates the appearance of the initial chat bubbles to a fourth appearance.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: Zoom Video Communications, Inc.Inventors: Oded Gal, Andrew Law, Sally Lu, Ping Luo, Sharvari Nerurkar, Archil Vardidze, Zheng Yuan
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11920157Abstract: Applications of butylidenephthalide (BP), comprising the use of BP in providing a kit for promoting differentiation of stem cells into brown adipose cells, and the use of BP in preparing a medicament, wherein the medicament is used for inhibiting the accumulation of white adipose cells, promoting the conversion of white adipose cells into brown adipose cells, inhibiting weight gain and/or reducing the content of triglycerides, glucose, and total cholesterol in blood.Type: GrantFiled: September 15, 2022Date of Patent: March 5, 2024Assignee: NATIONAL DONG HWA UNIVERSITYInventors: Tzyy-Wen Chiou, Shinn-Zong Lin, Horng-Jyh Harn, Hong-Lin Su, Shih-Ping Liu, Kang-Yun Lu, Jeanne Hsieh
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Publication number: 20240067631Abstract: Provided herein are compounds of formula (A): or a pharmaceutically acceptable salt thereof, wherein X, R1, R2, R3, R4, Ry, and Rz are as defined herein. Also provided herein is a pharmaceutically acceptable composition comprising a compound of formula (A), or a pharmaceutically acceptable salt thereof, as well as methods of using a compound of formula (A), or a pharmaceutically acceptable salt thereof, to treat various diseases and conditions mediated by nicotinamide phosphoribosyltransferase (NAMPT).Type: ApplicationFiled: December 20, 2021Publication date: February 29, 2024Inventors: Minxing SHEN, Antonio ROMERO, Pu-Ping LU
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Publication number: 20240069074Abstract: A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Ping LU, Shaishav A. DESAI, Minhan CHEN
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Patent number: 11907295Abstract: Provided is a method for reverse real-time matching based on event-driven graph patterns. The method includes definition of a graph pattern, establishment of reverse matching architecture and a reverse matching method; and the graph pattern is used for describing a spatial connection relationship among vertices and edges in a graph in a reverse order and attribute constraints thereof, and includes a linked list of matching steps and matching contexts. Reverse real-time matching of the graph pattern is realized according to the reverse matching architecture, and the problem of event-driven subgraph matching in a real-time scene is solved.Type: GrantFiled: July 17, 2022Date of Patent: February 20, 2024Assignee: ZHEJIANG BANGSUN TECHNOLOGY CO., LTD.Inventors: Xingen Wang, Xinyu Wang, Lu Jin, Wei Chen, Ping Lu, Yang Gao, Tao Huang
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Patent number: 11893327Abstract: System and method that allow utilize machine learning algorithms to move a micro-object to a desired position are described. A sensor such as a high speed camera or capacitive sensing, tracks the locations of the objects. A dynamic potential energy landscape for manipulating objects is generated by controlling each of the electrodes in an array of electrodes. One or more computing devices are used to: estimate an initial position of a micro-object using the sensor; generate a continuous representation of a dynamic model for movement of the micro-object due to electrode potentials generated by at least some of the electrodes and use automatic differentiation and Gauss quadrature rules on the dynamic model to derive optimum potentials to be generated by the electrodes to move the micro-object to the desired position; and map the calculated optimized electrode potentials to the array to activate the electrodes.Type: GrantFiled: December 14, 2020Date of Patent: February 6, 2024Assignee: XEROX CORPORATIONInventors: Ion Matei, Anne Plochowietz, Saigopal Nelaturi, Johan de Kleer, Jeng Ping Lu, Lara S. Crawford, Eugene M. Chow
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Publication number: 20240036534Abstract: Control loop latency can be accounted for in predicting positions of micro-objects being moved by using a hybrid model that includes both at least one physics-based model and machine-learning models. The models are combined using gradient boosting, with a model created during at least one of the stages being fitted based on residuals calculated during a previous stage based on comparison to training data. The loss function for each stage is selected based on the model being created. The hybrid model is evaluated with data extrapolated and interpolated from the training data to prevent overfitting and ensure the hybrid model has sufficient predictive ability. By including both physics-based and machine-learning models, the hybrid model can account for both deterministic and stochastic components involved in the movement of the micro-objects, thus increasing the accuracy and throughput of the micro-assembly.Type: ApplicationFiled: September 6, 2023Publication date: February 1, 2024Inventors: Anne Plochowietz, Anand Ramakrishnan, Warren Jackson, Lara S. Crawford, Bradley Rupp, Sergey Butylkov, Jeng Ping Lu, Eugene M. Chow
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Patent number: 11882797Abstract: An automatic detection and recovery device for residual agricultural mulch film, and a method of using the device, comprising a quadcopter, a wheeled robot (9), and a host computer (8); the quadcopter is provided with a controller (1), a near infrared water content analyzer, and a WiFi module that are used to measure water content in soil and communicate with the host computer; the wheeled robot (9) comprises a water sprinkling device (2), a soil grabbing device (3), a sifting device (4), a delivery device (5), a recognition device (6), and a sorting device (7).Type: GrantFiled: February 24, 2020Date of Patent: January 30, 2024Assignee: NANTONG UNIVERSITYInventors: Liang Hua, Zeguang Zhang, Jiahan You, Yisheng Huang, Ping Lu