Patents by Inventor Ping Mei

Ping Mei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200342280
    Abstract: Systems and methods for operating a tag system. The methods comprising: wirelessly communicating, from a tag, a first signal at a first frequency spectrum that allows a tag reader to detect the first signal, when the tag is not proximate to an antenna modulation marker or when the antenna modulation marker has a first orientation relative to the tag; and performing operations by the tag to wirelessly communicate a second signal at a second frequency spectrum that does not allow the tag reader to detect the first signal, when the tag is proximate to the antenna modulation marker or when the antenna modulation marker has a second different orientation relative to the tag.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Ping Mei, JengPing Lu, Kent Evans, Janos Veres
  • Patent number: 10818842
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 27, 2020
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20200282746
    Abstract: A system and method of printing on a strand element with a printer head. The printer head includes a conduit and a cavity formed within the conduit, wherein the cavity is configured to receive the strand element and pass the strand element from a first end of the cavity to a second end of the cavity. The printer head also includes a first set of fluid nozzles formed on the conduit and positioned on a perimeter of the cavity around a first target location within the cavity, wherein each of the fluid nozzles in the first set is positioned to aim at the first target location, and the first target location corresponds to a location of a first segment of the strand element when the strand element is positioned within the cavity.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: Ping Mei, Warren Jackson, Steven E. Ready
  • Patent number: 10628725
    Abstract: Systems and methods for operating a tag system. The methods comprise performing the following operations by a tag having an antenna: emitting a signal at a first frequency spectrum, if the tag is not proximate to a tag modulation marker; and emitting a signal at a second frequency spectrum, if the tag is proximate to the tag modulation marker.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 21, 2020
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Janos Veres
  • Patent number: 10571804
    Abstract: A method of fabricating a color filter array including providing substrate, forming a multilevel structure that is attached to the substrate, etching the multilevel structure to expose first wells in the multilevel structure, filling at least the first wells in the multilevel structure with the first color component, curing the first color component, etching the multilevel structure to expose second wells in the multilevel structure, filling at least the second wells in the multilevel structure with a second color component, and curing the second color component.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 25, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Carl P. Taussig, Edward Robert Holland, Ping Mei, Richard E. Elder
  • Publication number: 20200052214
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Application
    Filed: October 22, 2019
    Publication date: February 13, 2020
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 10490746
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 26, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 10466193
    Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 5, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Patent number: 10427397
    Abstract: Disclosed is a conformable, stretchable and electrical conductive structure, which includes an auxetic structure, and a plurality of electrical conductors. The plurality of electrical conductors being incorporated within the auxetic structure, to form conformable, stretchable electrical interconnects, configured based on a design of the auxetic structure and placement of the electrical conductors incorporated with the auxetic structure.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 1, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Corie Lynn Cobb, Steven E. Ready, John S. Paschkewitz
  • Patent number: 10420222
    Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: September 17, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Brent S. Krusor, Ping Mei
  • Patent number: 10388874
    Abstract: Electronic devices having two or more conductive contacts or terminals and methods of making the same. Including having a conducting interconnect line coated with an insulator stack (functionalized to be hydrophobic), cut—simultaneously allowing for one step, self-aligned, patterning of formed conducting contacts and the insulation stack. The combination of the cut in the insulation, along with the low surface energy of the insulating surface allow for active material to be deposited at the cut site defining the channel.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 20, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jonathan Rivnay, Ping Mei, Brent S. Krusor
  • Patent number: 10349528
    Abstract: A material deposition system and method is disclosed for depositing material onto raised features on a surface of a substrate. The material deposition system and method are a contact deposition or printing system and method, which employs biased rollerball to deposit the material as it travels along the substrate and over the raised features.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 9, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Brent S. Krusor, Ping Mei
  • Publication number: 20190124757
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 25, 2019
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 10229726
    Abstract: A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: March 12, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: David Eric Schwartz, Tse Nga Ng, Ping Mei
  • Patent number: 10206288
    Abstract: A hybrid electronic assembly includes a substrate having conductive circuit tracings, and includes at least one opening defined within length and width dimensions of the substrate. An electronic circuit component which has conductive circuit tracings, and is located within the at least one opening of the substrate. An alignment area where a first surface of the substrate and a first surface of the electronic circuit component are aligned in a substantially planar flat relationship with the electronic circuit component. A non-alignment area where a second surface of the substrate and a second surface of the electronic circuit component are in a non-aligned relationship.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 12, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Gregory L. Whiting, Brent S. Krusor
  • Patent number: 10199586
    Abstract: A process for preparing a device and a device including a substrate; an interlayer disposed on the substrate, wherein the interlayer comprises a cured film formed from an interlayer composition, wherein the interlayer composition comprises: an epoxy compound; a polyvinyl phenol; a melamine resin; a solvent; an optional surfactant; and an optional catalyst; a source electrode and a drain electrode disposed on a surface of the interlayer; a semiconductor layer disposed on the interlayer, wherein the semiconductor layer is disposed into a gap between the source and drain electrode; a back channel interface comprising an interface between the semiconductor layer and the interlayer, wherein the interlayer serves as a back channel dielectric layer for the device; a dielectric layer disposed on the semiconductor layer; a gate electrode disposed on the dielectric layer. Also an interlayer composition and an organic thin film transistor comprising the interlayer composition.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 5, 2019
    Assignees: Xerox Corporation, Palo Alto Research Center Incorporated
    Inventors: Guiqin Song, Ping Mei, Nan-Xing Hu, Gregory Whiting, Biby Esther Abraham
  • Patent number: 10165677
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: December 25, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Publication number: 20180350729
    Abstract: Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Brent S. Krusor, Steven E. Ready
  • Patent number: 10147702
    Abstract: The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 4, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Brent S. Krusor, Ping Mei
  • Patent number: 10141668
    Abstract: Printed flexible hybrid electronic systems may require electrical interconnection to peripheral elements. For example, a printed sensor tag with wireless communication may need to connect to a printed sensing electrode on a separated substrate. Frequently, it is desired that these interconnections be detachable in order to replace peripheral elements or to facilitate low cost and simplified assembly, test, rework, and repair. Unlike conventional printed circuit board, mounting a connector on a flexible substrate for detachable connection is challenging due to low temperature requirements. Provide is a teaching of a thin film or form of electrical connection for two circuit elements on separate flexible substrates. The connection is detachable and re-attachable for replacing different circuit elements. The detachable connection is in embodiments realized by selective deposition of fine patterns of conductive materials and non-conductive repositionable pressure-sensitive adhesive.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 27, 2018
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, David Eric Schwartz, Brent S. Krusor