Patents by Inventor Ping Mei

Ping Mei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180310415
    Abstract: Methods and system which eliminate steps in the mounting a discrete device to an electronic circuit using a conductive film, shortening the time required to attach each discrete device. The methods place a discrete device onto the conductive tape and partially cure portions of the adhesive. The discrete device is then removed from the conductive tape along with the adhesive and conductive particles which have been transferred onto the contact pads of the discrete device. The discrete device is then placed on the substrate and aligned. Pressure and heat are applied to complete the bond.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 25, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Brent S. Krusor, Ping Mei
  • Publication number: 20180284059
    Abstract: Electronic devices having two or more conductive contacts or terminals and methods of making the same. Including having a conducting interconnect line coated with an insulator stack (functionalized to be hydrophobic), cut—simultaneously allowing for one step, self-aligned, patterning of formed conducting contacts and the insulation stack. The combination of the cut in the insulation, along with the low surface energy of the insulating surface allow for active material to be deposited at the cut site defining the channel.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Jonathan Rivnay, Ping Mei, Brent S. Krusor
  • Publication number: 20180252659
    Abstract: A printed resistive gas detector configuration that is simple, inexpensive and compact, fabricated for incorporation into an electronic device, such as an electronic computing and/or communication device, the printed resistive gas detector configuration designed to continuously monitor for predetermined types of gasses. The printed resistive gas detector configuration manufactured by the use of printing technology to print on a flexible substrate.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Robert A. Street, David Eric Schwartz, Ping Mei, Brent S. Krusor, Jonathan Rivnay, Yong Zhang, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20180254302
    Abstract: A method and system utilizes ink jetting or printing of surface work function modification material or solution to form modified p-type and/or n-type electrodes. The proposed method is suitable for making complementary OTFT circuits in roll-to-roll fabrication environment.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Robert A. Street, Gregory L. Whiting, Sivkheng Kor, Steven E. Ready
  • Publication number: 20180236480
    Abstract: A material deposition system and method is disclosed for depositing material onto raised features on a surface of a substrate. The material deposition system and method are a contact deposition or printing system and method, which employs biased rollerball to deposit the material as it travels along the substrate and over the raised features.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Brent S. Krusor, Ping Mei
  • Publication number: 20180114772
    Abstract: The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a flexible substrate.
    Type: Application
    Filed: October 24, 2016
    Publication date: April 26, 2018
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Brent S. Krusor, Ping Mei
  • Patent number: 9952082
    Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 24, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
  • Patent number: 9947611
    Abstract: Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 17, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Brent S. Krusor, David K. Biegelsen
  • Publication number: 20180033982
    Abstract: A process for preparing a device and a device including a substrate; an interlayer disposed on the substrate, wherein the interlayer comprises a cured film formed from an interlayer composition, wherein the interlayer composition comprises: an epoxy compound; a polyvinyl phenol; a melamine resin; a solvent; an optional surfactant; and an optional catalyst; a source electrode and a drain electrode disposed on a surface of the interlayer; a semiconductor layer disposed on the interlayer, wherein the semiconductor layer is disposed into a gap between the source and drain electrode; a back channel interface comprising an interface between the semiconductor layer and the interlayer, wherein the interlayer serves as a back channel dielectric layer for the device; a dielectric layer disposed on the semiconductor layer; a gate electrode disposed on the dielectric layer. Also an interlayer composition and an organic thin film transistor comprising the interlayer composition.
    Type: Application
    Filed: July 28, 2016
    Publication date: February 1, 2018
    Applicants: Xerox Corporation, Palo Alto Research Center Incorporated
    Inventors: Guiqin Song, Ping Mei, Nan-Xing Hu, Gregory Whiting, Biby Esther Abraham
  • Patent number: 9874984
    Abstract: Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 23, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Janos Veres
  • Patent number: 9853230
    Abstract: A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 26, 2017
    Assignees: XEROX CORPORATION, PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Tse Nga Ng, Ping Mei, Yiliang Wu, Biby Esther Abraham
  • Publication number: 20170328761
    Abstract: The level sensor system includes a level sensor label configured to be associated with a container containing a material whose level is to be sensed, the level sensor label arrangement having a circuit which includes an inductive element electrically connected to a capacitive structure configured to be associated with the container.
    Type: Application
    Filed: May 10, 2016
    Publication date: November 16, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: David E. Schwartz, Yunda Wang, Robert A. Street, Ping Mei, Janos Veres, Gregory L. Whiting, Steven E. Ready, Tse Nga Ng
  • Publication number: 20170221795
    Abstract: Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 3, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Brent S. Krusor, David K. Biegelsen
  • Publication number: 20170215284
    Abstract: Disclosed is a conformable, stretchable and electrical conductive structure, which includes an auxetic structure, and a plurality of electrical conductors. The plurality of electrical conductors being incorporated within the auxetic structure, to form conformable, stretchable electrical interconnects, configured based on a design of the auxetic structure and placement of the electrical conductors incorporated with the auxetic structure.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 27, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Ping Mei, Corie Lynn Cobb, Steven E. Ready, John S. Paschkewitz
  • Publication number: 20170171958
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed.
    Type: Application
    Filed: December 10, 2015
    Publication date: June 15, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Tse Nga Ng, Ping Mei, Brent S. Krusor, Gregory L. Whiting, Steven E. Ready, Janos Veres
  • Patent number: 9629252
    Abstract: A circuit can include a pre-patterned substrate having a supporting material, multiple segments thereon, and interdigitated line structures within each segment. Some of the line structures can be bundled together, and an electrical component can be formed by ink jetting onto the bundled line structures.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: April 18, 2017
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Tse Nga Ng, Gregory Whiting
  • Publication number: 20170102611
    Abstract: A method of fabricating a color filter array including providing substrate, forming a multilevel structure that is attached to the substrate, etching the multilevel structure to expose first wells in the multilevel structure, filling at least the first wells in the multilevel structure with the first color component, curing the first color component, etching the multilevel structure to expose second wells in the multilevel structure, filling at least the second wells in the multilevel structure with a second color component, and curing the second color component.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 13, 2017
    Inventors: Carl P. TAUSSIG, Edward Robert HOLLAND, Ping MEI, Richard E. ELDER
  • Publication number: 20170090613
    Abstract: Touch user interfaces have been an essential element in the use of smartphones and tablets. An improved touch or near touch sensing structure made of a printed conductive double-wrapped coil is disclosed. A printable substrate is used to provide a base for the double-wrapped coil. On the printable substrate, a double-wrapped coil is printed using at least one flexible conductive material. The double-wrapped coils can be printed sequentially, simultaneously, parts of the two coils are printed and then the rest of the coil parts are printed, or any other useful printing order. The double-wrapped coil provides an increased sensing area and therefore can compute a more efficient capacitance.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Tse Nga Ng, Janos Veres
  • Patent number: 9583387
    Abstract: Circuit fabrication uses a multilevel mask to pattern a first conductor layer of a multilayer circuit. The first conductor patterning is to provide electrical isolation between the first conductor layer and a second conductor layer that one of overlies the multilevel mask and underlies the multilevel mask. With the second conductor layer overlying the multilevel mask, the electrical isolation is provided by undercutting the multilevel mask. Alternatively, with the second conductor underlying the multilevel mask, the first conductor includes a bridged gapped conductor and the electrical isolation may be provided by both the bridged gapped conductor and an insulating layer between the second conductor layer and the first conductor layer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: February 28, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ping Mei, Carl A. Taussig, Marcia Almanza-Workman
  • Publication number: 20170048986
    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among others, where the surface of the electronic circuit component is at the same level as the associated substrate, the surface of the electronic circuit component holding connection pads. A gap exists between the electronic circuit component, and the end of an opening within the substrate. This gap is filled with a filler material, such as a bonding material. The bonding material also used to encapsulate or bond together the back side of the substrate and electronic circuit component. During the manufacturing process, the front surface of the electronic circuit component (which includes the contact pads) and the front surface of the substrate which includes electronic circuitry are held in an adhesive relationship by a flat material having an upper surface which includes adhesive or sticky material (such as PDMS).
    Type: Application
    Filed: December 10, 2015
    Publication date: February 16, 2017
    Applicant: Palo Alto Research Center Incorporated
    Inventors: Ping Mei, Gregory L. Whiting, Brent S. Krusor