Abstract: A method of fabricating a color filter array including providing substrate, forming a multilevel structure that is attached to the substrate, etching the multilevel structure to expose first wells in the multilevel structure, filling at least the first wells in the multilevel structure with the first color component, curing the first color component, etching the multilevel structure to expose second wells in the multilevel structure, filling at least the second wells in the multilevel structure with a second color component, and curing the second color component.

Abstract: A memory circuit has a ferroelectric memory cell having a word line and a bit line, an input transistor connected to the bit line, a gain element electrically connected the bit line, wherein the gain element includes a feedback capacitor, and an output terminal. A method of reading a memory cell includes applying a voltage to a word line of the memory cell, causing charge to transfer from the memory cell to a feedback capacitor, generating a voltage, amplifying the voltage by applying a gain having a magnitude of less than three, sensing an output voltage at an output node to determine a state of the memory cell, and storing the memory state in a latch.

Abstract: A system and method is used to optimize print parameters in the printing of functional electronic materials and integrated objects. The method employs a grid pattern to determine drop spacing and further assigns priority to various features to be printed, separating features into layers to be printed. The most critical layers being printed with higher resolution and greater accuracy, the less critical layers being printed at lower resolution.

Abstract: A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.

Abstract: A pre-patterned substrate has a supporting material, a plurality of segments on the supporting material, a plurality of interdigitated line structures within each segment to allow formation of features, and an isolation region between the segments.

Abstract: A circuit can include a pre-patterned substrate having a supporting material, multiple segments thereon, and interdigitated line structures within each segment. Some of the line structures can be bundled together, and an electrical component can be formed by ink jetting onto the bundled line structures.

Abstract: Circuit fabrication uses a multilevel mask to pattern a first conductor layer of a multilayer circuit. The first conductor patterning is to provide electrical isolation between the first conductor layer and a second conductor layer that one of overlies the multilevel mask and underlies the multilevel mask. With the second conductor layer overlying the multilevel mask, the electrical isolation is provided by undercutting the multilevel mask. Alternatively, with the second conductor underlying the multilevel mask, the first conductor includes a bridged gapped conductor and the electrical isolation may be provided by both the bridged gapped conductor and an insulating layer between the second conductor layer and the first conductor layer.

Abstract: A pre-patterned substrate has a supporting material, a plurality of segments on the supporting material, a plurality of interdigitated line structures within each segment to allow formation of features, and an isolation region between the segments.

Abstract: An electronic apparatus is provided that includes a number of first components on a first substrate and a number of second components on a second substrate. A lamination material that includes a conducting material is placed between the first components and the second components. Any one first component can couple to a varied subset of second components.

Abstract: A method of fabricating a color filter array including providing substrate, forming a multilevel structure that is attached to the substrate, etching the multilevel structure to expose first wells in the multilevel structure, filling at least the first wells in the multilevel structure with the first color component, curing the first color component, etching the multilevel structure to expose second wells in the multilevel structure, filling at least the second wells in the multilevel structure with a second color component, and curing the second color component.

Abstract: This invention provides a thin film device with minimized spatial variation of local mean height. More specifically, the thin film device has a substrate and at least one first structure having a first spatially varying weighted local mean height determined by a layer weighting function. The first structure has a first maximum height, a first minimum height and a first variation for a given averaging area. A compensation structure is also provided upon the substrate, the compensation structure having a second spatially varying weighted local mean height determined by the layer weighting function. The compensation structure also has a second maximum height, a second minimum height and a second variation for the given averaging area. The first structure and compensation structure combine to provide a combined structure upon the substrate with minimized spatial variation of a combined weighted local mean.

Abstract: Example embodiments disclosed herein relate to display outputting a user interface.

Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.

Abstract: A tactile display for providing tactile feedback has a touch surface layer formed of a plurality of pixels. Each pixel has an aperture for ejecting a fluid, and a valve for opening and closing the aperture. The valve is operable to modulate the fluid ejection through the aperture at a frequency selected for detection by the somatic sensors of a human finger.

Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.

Abstract: The present invention includes a method and system for forming a semiconductor device. Varying embodiments generate 2 dimensional alignment features in a device by implementing a 3-dimensional pattern into an underlying device substrate. Accordingly, alignments between successive device patterning steps can be determined regardless of the dilations or contractions that can take place during the device fabrication process. A first aspect of the present invention is a method for forming a semiconductor device. The method includes forming a 3-dimensional pattern in a substrate and depositing at least one material over the substrate in accordance with desired characteristics of the semiconductor device.

Abstract: An electronic apparatus is provided that includes a number of first components on a first substrate and a number of second components on a second substrate. A lamination material that includes a conducting material is placed between the first components and the second components. Any one first component can couple to a varied subset of second components.

Abstract: Provided is a low cost system and method for forming electronic devices, especially large surface area devices. The process of imprint lithography is combined with alternate manufacturing techniques to fabricate the devices. Initially, a template imprints a three-dimensional pattern into a resist layer deposited on a flexible substrate. The resist layer is cured using ultraviolet light or other curing techniques. After curing, the 3-D pattern is modified using one of several techniques to include inkjetting, electrodeposition or laser patterning. In one embodiment, a semi-fluid material may be jetted into channels formed in the pattern, thereby forming conductive or insulating lead lines. Alternatively, a two-dimensional pattern may be jetted onto the resist layer. Final processing may include multiple etch-mask-etch steps. The integration of techniques into a single system provides a low cost, efficient method for manufacturing high quality, large surface area electronic devices.

Abstract: A tactile display has a contact surface that has multiple addressable pixels. Each pixel has a vibration element that is energizable to vibrate at a selected frequency and amplitude. The vibration of selected pixels of the tactile display provides tactile feedback to a user's finger touching the contact surface.

Abstract: A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.