Patents by Inventor Ping Ping

Ping Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250184818
    Abstract: Embodiments of the present disclosure relate to voice packet combination. A terminal device receives, from a network device, control information for controlling voice packet combining at the terminal device, and determines the voice packet combining based on the control information, and then the terminal device performs the voice packet combining; and transmits the combined voice packet to the network device. The solution enables the network to control the packet combining in terminal device based on control information.
    Type: Application
    Filed: August 10, 2022
    Publication date: June 5, 2025
    Inventors: Ping YUAN, Ping Ping WEN
  • Publication number: 20250055608
    Abstract: Example embodiments of the present disclosure relate to a terminal device, a network device, methods, apparatuses, and a computer readable storage medium for HARQ state for RRC configuration for multi-TB scheduling. In the solution, a terminal device may receive information which schedules multiple TBs and indicating multiple HARQ processes, the terminal device may further determine a same HARQ state for all of the multiple HARQ processes based on a configured HARQ state of a specific HARQ process in the multiple HARQ processes. As such, a same HARQ state may be applied for all scheduled TBs. Therefore, a flexibility on scheduling is provided, in addition, the DRX behavior for multi-TB scheduling is simplified.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 13, 2025
    Inventors: Ping Ping WEN, Ping YUAN, Jing Yuan SUN, Tzu-Chung HSIEH
  • Publication number: 20250056562
    Abstract: Embodiments of the present disclosure relate to an indication associated with PDCCH monitoring. In an aspect, a terminal device receives from a network device, downlink control information (DCI) comprising an indication of an operation associated with at least one of physical downlink control channel (PDCCH) monitoring or discontinuous reception (DRX). The terminal device performs the operation based on the indication. The embodiments of the present disclosure can provide more flexibility on scheduling and can save power consumption.
    Type: Application
    Filed: August 7, 2024
    Publication date: February 13, 2025
    Inventors: Ping Ping WEN, Ping YUAN, Jing Yuan SUN, Tzu-Chung HSIEH
  • Publication number: 20250013802
    Abstract: The present disclosure provides a coupling network model lithium-ion battery energy storage system fire spread modeling method, which belongs to the technical field of lithium-ion battery model construction and simulation method.
    Type: Application
    Filed: July 30, 2023
    Publication date: January 9, 2025
    Applicant: China University of Petroleum (East China)
    Inventors: Depeng KONG, Gongquan WANG, Ping PING
  • Publication number: 20240395722
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Publication number: 20240386167
    Abstract: The invention discloses a modeling method for energy storage tank explosion venting to prevent thermal runaway gas explosion in lithium-ion batteries, which relates to the technical field of lithium-ion battery energy storage tank design, including the following steps: 1. Determine lithium-ion battery type to obtain component classification and ratio of mixed gas produced after thermal runaway; 2. Calculate laminar burning velocity of mixed gas and thermophysical parameters using FreeFlam 1D combustion model; 3. Set coupling boundary of venting plate, divide premixed area inside the tank and the air area outside the tank, establish geometric modeling and grid of battery energy storage tank, and establish three-dimensional combustion process equation according to the boundary conditions; 4. Solve three-dimensional combustion process equation to obtain the evolution characteristics of overpressure, temperature, and wind speed in the internal and external flow fields of energy storage tank.
    Type: Application
    Filed: June 14, 2023
    Publication date: November 21, 2024
    Applicant: CHINA UNIVERSITY OF PETROLEUM (east CHINA)
    Inventors: Depeng KONG, Rongqi PENG, Ping PING
  • Patent number: 12142570
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Patent number: 12002793
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: June 4, 2024
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Patent number: 11837458
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Publication number: 20230048835
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 16, 2023
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Patent number: 11521932
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 6, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Patent number: 11355458
    Abstract: A device and method of utilizing conductive thread interconnect cores. Substrates using conductive thread interconnect cores are shown. Methods of creating a conductive thread interconnect core are shown.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Publication number: 20220102295
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Application
    Filed: October 11, 2021
    Publication date: March 31, 2022
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Patent number: 11237822
    Abstract: Embodiments of the present invention provide a computer-implemented method for generating an API difference description file that describes the differences between multiple API versions to assist in migrating an application program from a first version to a second version. The method includes receiving a first API description file of a first version of a web API, receiving a second API description file of a second version of the web API, generating an API difference description file that describes differences between the first and second API description files, and then updating an application program using the API difference description file.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guo Qiang Li, Cheng Fang Wang, Ping Ping Cheng, Zhen Zhang, Chang Ning Song
  • Publication number: 20210366883
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 25, 2021
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Patent number: 11164827
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Patent number: 11121074
    Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
  • Patent number: 11114421
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Publication number: 20210183776
    Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
    Type: Application
    Filed: September 18, 2020
    Publication date: June 17, 2021
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Ping Ping Ooi, Seok Ling Lim
  • Patent number: D1023592
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 23, 2024
    Assignee: PING EXPEDIA
    Inventor: Ping Ping Ang