Patents by Inventor Ping Ping

Ping Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10388636
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Patent number: 10317938
    Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eng Huat Goh, Khai Ern See, Damien Weng Kong Chong, Min Suet Lim, Ping Ping Ooi, Chu Aun Lim, Jimmy Huat Since Huang, Poh Tat Oh, Teong Keat Beh, Jackson Chung Peng Kong, Fern Nee Tan, Jenn Chuan Cheng
  • Publication number: 20190068435
    Abstract: According to an embodiment of the present disclosure, there is provided a method for a distributed transaction processing environment. The method includes in response to determining that a state of a first node acting as a first coordinating node is not performing properly, selecting a second node from a first plurality of participating nodes communicatively coupled to the first node. The method further includes activating the selected second node to be a second coordinating node while deactivating the first node to be a participating node. In addition, the method includes performing a transaction based on a cooperation between the first and second nodes.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Inventors: PING PING CHENG, JUN HUA GAO, GUAN JUN LIU, XUE YONG ZHANG, BEI CHUN ZHOU, XI BO ZHU
  • Publication number: 20190068436
    Abstract: According to an embodiment of the present disclosure, there is provided a method for a distributed transaction processing environment. The method includes in response to determining that a state of a first node acting as a first coordinating node is not performing properly, selecting a second node from a first plurality of participating nodes communicatively coupled to the first node. The method further includes activating the selected second node to be a second coordinating node while deactivating the first node to be a participating node. In addition, the method includes performing a transaction based on a cooperation between the first and second nodes.
    Type: Application
    Filed: November 27, 2017
    Publication date: February 28, 2019
    Inventors: PING PING CHENG, JUN HUA GAO, GUAN JUN LIU, XUE YONG ZHANG, BEI CHUN ZHOU, XI BO ZHU
  • Publication number: 20190056872
    Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Ping, Sai Rahul Chalamalasetti, Andrew C. Walton
  • Publication number: 20190006277
    Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
    Type: Application
    Filed: June 25, 2018
    Publication date: January 3, 2019
    Inventors: Bok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
  • Publication number: 20180366407
    Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage.
    Type: Application
    Filed: May 17, 2018
    Publication date: December 20, 2018
    Applicant: Intel Corporation
    Inventors: Ping Ping OOI, Bok Eng CHEAH, Jackson Chung Peng KONG, Mooi Ling CHANG, Wen Wei LUM
  • Publication number: 20180358292
    Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.
    Type: Application
    Filed: May 8, 2018
    Publication date: December 13, 2018
    Applicant: Intel Corporation
    Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Wen Wei LUM, Mooi Ling CHANG, Ping Ping OOI
  • Publication number: 20180349245
    Abstract: A computer-implemented method, a computer program product, and a computer system for parallel task management. A computer system receives a new task that requests to access a resource may be received. In response to an access workload being above a first threshold, the computer system dispatches the new task to at least one predefined processing unit, wherein the access workload may be associated with the resource that is in parallel accessed by a plurality of existing tasks.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Xi Bo Zhu, Bei Chun Zhou
  • Publication number: 20180349246
    Abstract: A computer program product and a computer system for parallel task management. A computer system receives a new task that requests to access a resource may be received. In response to an access workload being above a first threshold, the computer system dispatches the new task to at least one predefined processing unit, wherein the access workload may be associated with the resource that is in parallel accessed by a plurality of existing tasks.
    Type: Application
    Filed: October 31, 2017
    Publication date: December 6, 2018
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Xi Bo Zhu, Bei Chun Zhou
  • Publication number: 20180331081
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Patent number: 10109323
    Abstract: A method of controlling a computing device includes detecting a user input request to disengage a drive component from a computing device, the computing device comprising a multiple-drive storage system having a plurality of drive components forming a single logical unit, and determining whether or not disengaging the drive component would cause failure of the multiple-drive storage system. The method includes disallowing disengagement of the drive component from the computing device in response to determining that disengaging the drive component would cause failure of the multiple-drive storage system, and allowing disengagement of the drive component from the computing device in response to determining that disengaging the drive component would not cause failure of the multiple-drive storage system.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: October 23, 2018
    Assignee: Lenovo Enterprise Solutions (Singapore) PTE. LTD.
    Inventors: Chekim Chhuor, Liying Jin, Ping Ping Zhao, Yu Yu
  • Publication number: 20180294252
    Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
    Type: Application
    Filed: November 5, 2015
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Bok Eng CHEAH, Jackson Chung Peng KONG, Ping Ping OOI, Kooi Chi OOI, Shanggar PERIAMAN
  • Publication number: 20180226357
    Abstract: A semiconductor package is disclosed. The semiconductor package includes a multilayer package substrate. The layers of the multi-layer substrate include one or more conductive layers to transmit information within the semiconductor package. The layers also include one or more conductive power supply layers to provide power to the semiconductor package and to one or more connected components. The layers also include one or more layers of dielectric material forming a substrate core dielectric. The layers also include an embedded reference plane within the substrate core dielectric, wherein the embedded reference plane is conductive and reduces electrical interference between the other conductive layers in the multilayer package substrate.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 9, 2018
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Paik Wen Ong, Kooi Chi Ooi
  • Publication number: 20170345462
    Abstract: A method of controlling a computing device includes detecting a user input request to disengage a drive component from a computing device, the computing device comprising a multiple-drive storage system having a plurality of drive components forming a single logical unit, and determining whether or not disengaging the drive component would cause failure of the multiple-drive storage system. The method includes disallowing disengagement of the drive component from the computing device in response to determining that disengaging the drive component would cause failure of the multiple-drive storage system, and allowing disengagement of the drive component from the computing device in response to determining that disengaging the drive component would not cause failure of the multiple-drive storage system.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Inventors: CHEKIM CHHUOR, LIYING JIN, PING PING ZHAO, YU YU
  • Patent number: 9704654
    Abstract: Supercapacitor is an energy storage device with high power density and low energy density, and is normally used with a battery to satisfy one's needs for high power density and high energy density. The present invention provides a method to fabricate a novel battery type supercapacitor, with a multi-layered structure composed of a plurality of thin layers which is formed by alternately stacking high specific energy battery material and/or supercapacitor material such as metal oxides, metal hydroxides, metal sulfides, conductive polymers, carbon materials with reduced graphene oxide (rGO), to obtain a supercapacitor with both high specific energy density and high specific power density.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: July 11, 2017
    Assignee: SOUTHWEST UNIVERSITY
    Inventors: Chang Ming Li, Ping Ping Yang, Jia Le Xie
  • Publication number: 20170086298
    Abstract: Techniques and mechanisms to provide interconnect structures of a substrate such as a printed circuit board. In an embodiment, a first side of a substrate has disposed thereon a hardware interface contacts to couple the substrate to a packaged IC device. The contacts define a footprint area, where an overlap region of the substrate is defined by a projection of the footprint area from the first side to a second side of the substrate. The substrate forms a recess extending from one of the first side and the second side. In another embodiment, at least part of the recess is within the overlap region, and interconnect structures of the substrate facilitate connection between the packaged IC device and a capacitor disposed at least partially in the recess. Positioning of the capacitor within the overlap region enables improvements in substrate space efficiency, power delivery and/or signal noise.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 23, 2017
    Inventors: Tin Poay Chuah, Min Suet Lim, Ping Ping Ooi, Eng Huat Goh, See Chin Chow
  • Patent number: 9543244
    Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Chung Peng Jackson Kong, Chang-Tsung Fu, Telesphor Kamgaing, Chan Kim Lee, Ping Ping Ooi
  • Publication number: 20160216731
    Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Eng Huat Goh, Khai Ern See, Damien Weng Kong Chong, Min Suet Lim, Ping Ping Ooi, Chu Aun Lim, Jimmy Huat Since Huang, Poh Tat Oh, Teong Keat Beh, Jackson Chung Peng Kong, Fern Nee Tan, Jenn Chuan Cheng
  • Publication number: 20160086740
    Abstract: Supercapacitor is an energy storage device with high power density and low energy density, and is normally used with a battery to satisfy one's needs for high power density and high energy density. The present invention provides a method to fabricate a novel battery type supercapacitor, with a multi-layered structure composed of a plurality of thin layers which is formed by alternately stacking high specific energy battery material and/or supercapacitor material such as metal oxides, metal hydroxides, metal sulfides, conductive polymers, carbon materials with reduced graphene oxide (rGO), to obtain a supercapacitor with both high specific energy density and high specific power density.
    Type: Application
    Filed: February 16, 2015
    Publication date: March 24, 2016
    Inventors: Chang Ming LI, Ping Ping YANG, Jia Le XIE