Abstract: A steam physiotherapy apparatus includes an open-topped physiotherapy chamber having a door, a steam generating unit, and a steam pipe for conveying generated steam into the physiotherapy chamber. Tourmaline tiles are attached to an inner surface of the physiotherapy chamber, a steam inlet pipe is provided on a bottom of the physiotherapy chamber to communicate with the steam pipe, and a steam flow guide plate is placed on the steam inlet pipe. The steam inlet pipe has two diametrically opposite steam outlets directed to two opposite directions, such that the steam flowing out of the two steam outlets forms a swirl that moves upward along the inner surface of the physiotherapy chamber to heat the tourmaline tiles. The heated tourmaline tiles release far infrared rays and negative ions that help reducing reactive oxygen species and free radicals in the user's body and help the user to give off deep-layer sweat.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: A steam physiotherapy apparatus includes an open-topped physiotherapy chamber having a door, a steam generating unit, and a steam pipe for conveying generated steam into the physiotherapy chamber. Tourmaline tiles are attached to an inner surface of the physiotherapy chamber, a steam inlet pipe is provided on a bottom of the physiotherapy chamber to communicate with the steam pipe, and a steam flow guide plate is placed on the steam inlet pipe. The steam inlet pipe has two diametrically opposite steam outlets directed to two opposite directions, such that the steam flowing out of the two steam outlets forms a swirl that moves upward along the inner surface of the physiotherapy chamber to heat the tourmaline tiles. The heated tourmaline tiles release far infrared rays and negative ions that help reducing reactive oxygen species and free radicals in the user's body and help the user to give off deep-layer sweat.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: The present invention provides compositions and methods of their use for treating or preventing climacteric symptoms such as hot flashes. A composition of the invention preferably comprises Chaihu, Yujin, Mudanpi, Zicao, Baiwei, Baishao and Wuweizi or extracts thereof, and is preferably administered as a single composition.

Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract: A porous poly(2-acryl-amido-2-methyl-propane sulphonic acid)-based humidity sensing element is disclosed which provides improved range of humidity measurement and response time with little or no hysteresis. It includes: (a) a non-conductive substrate which has a pair of electrodes formed thereon; (b) a porous poly(2-acryl-amido-2-methyl-propane sulphonic acid) film formed on said electrodes. The porous poly(2-acryl-amido-2-methyl-propane sulphonic acid) film is formed by first forming a non-porous poly(2-acryl-amido-2-methyl-propane sulphonic acid) film on the electrodes, then subjecting the non-porous poly(2-acryl-amido-2-methyl-propane sulphonic acid) film to a heat treatment at temperatures between about 170° C. and 240° C. such that a porous structure is formed in said poly(2-acryl-amido-2-methyl-propane sulphonic acid) film.

Abstract: A method for forming a solid state humidity sensor is disclosed which comprises the steps of: (a) dissolving a tungstate salt into an aqueous solution; (b) adjusting the pH of the aqueous tungstate salt solution to below 8.5; (c) forming one or a pair of electrodes on an insulating substrate; (d) placing the substrate into the pH-adjusted aqueous tungstate salt solution and heating the aqueous solution containing the substrate at temperatures above 70.degree. C. to thereby form a pyrochlore-type crystalline tungsten trioxide film over the electrode or pair of electrodes; and (e) forming another electrode over the pyrochlore-type crystalline tungsten trioxide film if only one electrode is formed during step (c).

Abstract: A method for forming a solid state humidity sensor is disclosed which comprises the steps of: (a) dissolving a tungstate salt into an aqueous solution; (b) adjusting the pH of the aqueous tungstate salt solution to below 8.5; (c) forming one or a pair of electrodes on an insulating substrate; (d) placing the substrate into the pH-adjusted aqueous tungstate salt solution and heating the aqueous solution containing the substrate at temperatures above 70.degree. C. to thereby form a pyrochlore-type crystalline tungsten trioxide film over the electrode or pair of electrodes; and (e) forming another electrode over the pyrochlore-type crystalline tungsten trioxide film if only one electrode is formed during step (c).

Abstract: A gas sensor that has its heater and sensing layer on opposite sides of the substrate. The gas sensor includes a buffer layer separating the gas-sensing layer from the substrate to improve mechanical strength and electrical properties. The heater is preferably formed of nickel paste and is provided on the back of the substrate.

Abstract: A method of fabricating a gas sensor which comprises a substrate; a buffer layer coated on the substrate; at least one gas sensing layer arranged on the buffer layer; a pair of electrodes disposed on the gas sensing layer; and a catalytic layer coated on the gas sensing layer. A spin coating process is performed, using centrifugal force, to form the layers which are thin and evenly deposited on the substrate. The gas sensing layer of the gas sensor is formed before forming the electrodes of the same such that the heat treatment thereto can be carried out at 800.degree. C. which is much higher than the conventional temperature of 600.degree. C. The bonding of the gas sensing layer to the substrate is thereby much stronger than the conventional gas sensor.