Patents by Inventor Ping Ping

Ping Ping has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998261
    Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Wen Wei Lum, Mooi Ling Chang, Ping Ping Ooi
  • Patent number: 10980108
    Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Ping Ping Ooi, Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 10916524
    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Patent number: 10897534
    Abstract: Embodiments of the invention provide methods, systems, computer program products for managing a call waiting in a queue during a request for staff services provided by a call center. According to the method, a first voice segment received in a call made by a device is recorded first. Next, whether a part of the first voice segment is related to a first predefined voice segment is determined. The volume of device is adjusted in response to the part of the first voice segment being related to the first predefined voice segment. A user of the device is alerted in response to the part of the first voice segment being not related to the first predefined voice segment.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Guang Han Sui, Peng Hui Jiang, Qin Li, Ping Xiao, Niao Qing Liu, Xiang Zhou, Ping Ping Cheng
  • Publication number: 20210005547
    Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
    Type: Application
    Filed: March 16, 2020
    Publication date: January 7, 2021
    Inventors: Bok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
  • Patent number: 10698785
    Abstract: A computer-implemented method, a computer program product, and a computer system for parallel task management. A computer system receives a new task that requests to access a resource may be received. In response to an access workload being above a first threshold, the computer system dispatches the new task to at least one predefined processing unit, wherein the access workload may be associated with the resource that is in parallel accessed by a plurality of existing tasks.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Xi Bo Zhu, Bei Chun Zhou
  • Patent number: 10666495
    Abstract: According to an embodiment of the present disclosure, there is provided a method for a distributed transaction processing environment. The method includes in response to determining that a state of a first node acting as a first coordinating node is not performing properly, selecting a second node from a first plurality of participating nodes communicatively coupled to the first node. The method further includes activating the selected second node to be a second coordinating node while deactivating the first node to be a participating node. In addition, the method includes performing a transaction based on a cooperation between the first and second nodes.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Bei Chun Zhou, Xi Bo Zhu
  • Patent number: 10666496
    Abstract: According to an embodiment of the present disclosure, there is provided a method for a distributed transaction processing environment. The method includes in response to determining that a state of a first node acting as a first coordinating node is not performing properly, selecting a second node from a first plurality of participating nodes communicatively coupled to the first node. The method further includes activating the selected second node to be a second coordinating node while deactivating the first node to be a participating node. In addition, the method includes performing a transaction based on a cooperation between the first and second nodes.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ping Ping Cheng, Jun Hua Gao, Guan Jun Liu, Xue Yong Zhang, Bei Chun Zhou, Xi Bo Zhu
  • Patent number: 10593618
    Abstract: A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Mooi Ling Chang, Ping Ping Ooi, Jackson Chung Peng Kong, Wen Wei Lum
  • Publication number: 20200084880
    Abstract: A multi-conductor interconnect for a microelectronic device incorporates multiple conductors and integrated shielding for the conductors. The multi-conductor interconnect includes first and second groups of conductors interleaved with one another within a dielectric structure. One of the groups of conductors may be coupled to a reference voltage node to provide shielding for the other group of conductors. The multi-conductor interconnect may further include a shield layer extending over some portion, or all, of the conductors of the first and second groups.
    Type: Application
    Filed: November 22, 2017
    Publication date: March 12, 2020
    Inventors: Ping Ping Ooi, Bok Eng Cheah, Jackson Chung Peng Kong, Kool Chi Ooi
  • Publication number: 20200083194
    Abstract: Discussed generally herein are devices that can include multiple stacked dice electrically coupled to dice electrically coupled to a peripheral sidewall of the stacked dice and/or a dice stack electrically coupled to a passive die. In one or more embodiments a device can include a dice stack comprising at least two dice including a first die and a second die, the first die electrically connected to and on a second die, a first side pad on, or at least partially in, a first sidewall of the dice stack, a third die electrically connected to the first die at a first surface of the third die and through the first side pad, and a fourth die electrically connected to the third die at a second surface of the first die, the second side opposite the first side.
    Type: Application
    Filed: November 29, 2017
    Publication date: March 12, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Publication number: 20200050446
    Abstract: Embodiments of the present invention provide a computer-implemented method for generating an API difference description file that describes the differences between multiple API versions to assist in migrating an application program from a first version to a second version. The method includes receiving a first API description file of a first version of a web API, receiving a second API description file of a second version of the web API, generating an API difference description file that describes differences between the first and second API description files, and then updating an application program using the API difference description file.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Guo Qiang Li, Cheng Fang Wang, Ping Ping Cheng, Zhen Zhang, Chang Ning Song
  • Publication number: 20200027813
    Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a base package, an ancillary package, and an electrically isolated metal layer. The base package may include a base die. The ancillary package may include an ancillary component. The ancillary package may be located on top of the base package. The electrically isolated metal layer may be located at least partially within a layer of the base package such that a portion of the electrically isolated metal layer contacts at least one surface of the base die and is located in between the base die and the ancillary component.
    Type: Application
    Filed: June 26, 2019
    Publication date: January 23, 2020
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Kooi Chi Ooi, Ping Ping Ooi
  • Patent number: 10541200
    Abstract: Over-molded IC package assemblies including an embedded voltage reference plane and/or heat spreader. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more conductive layers are embedded within the molding compound. The conductive layers may include an interior portion located over the IC chip and a peripheral portion located over the redistribution layers or package substrate. The interior portion may comprise one or more heat conductive features, which may physically contact a surface of the IC chip. In some further embodiments, the peripheral portion comprises one or more electrically conductive features, which may physically contact a surface of the package redistribution layers or package substrate to convey a reference voltage.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: Ping Ping Ooi, Bok Eng Cheah, Jackson Chung Peng Kong, Mooi Ling Chang, Wen Wei Lum
  • Patent number: 10509642
    Abstract: Embodiments of the present invention provide a computer-implemented method for generating an API difference description file that describes the differences between multiple API versions to assist in migrating an application program from a first version to a second version. The method includes receiving a first API description file of a first version of a web API, receiving a second API description file of a second version of the web API, generating an API difference description file that describes differences between the first and second API description files, and then updating an application program using the API difference description file.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guo Qiang Li, Cheng Fang Wang, Ping Ping Cheng, Zhen Zhang, Chang Ning Song
  • Publication number: 20190378828
    Abstract: Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: August 20, 2019
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventors: Eng Huat Goh, Wee Hoe, Khang Choong Yong, Ping Ping Ooi
  • Publication number: 20190355681
    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.
    Type: Application
    Filed: December 19, 2017
    Publication date: November 21, 2019
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
  • Publication number: 20190311978
    Abstract: A semiconductor package substrate includes a composite and stacked vertical interconnect on a land side of the substrate. The composite and stacked vertical interconnect includes a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.
    Type: Application
    Filed: February 20, 2019
    Publication date: October 10, 2019
    Inventors: Bok Eng Cheah, Ping Ping Ooi, Shaw Fong Wong, Jackson Chung Peng Kong, Hungying Lo
  • Publication number: 20190303135
    Abstract: Embodiments of the present invention provide a computer-implemented method for generating an API difference description file that describes the differences between multiple API versions to assist in migrating an application program from a first version to a second version. The method includes receiving a first API description file of a first version of a web API, receiving a second API description file of a second version of the web API, generating an API difference description file that describes differences between the first and second API description files, and then updating an application program using the API difference description file.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Guo Qiang Li, Cheng Fang Wang, Ping Ping Cheng, Zhen Zhang, Chang Ning Song
  • Patent number: 10403604
    Abstract: Embodiments of the present disclosure are directed toward a stacked package assembly for embedded dies and associated techniques and configurations. In one embodiment, stacked package assembly may comprise a first die package and a second die package stacked one upon the other with plural interconnections between them; and a voltage reference plane embedded in at least one of the first and second die packages in proximity and generally parallel to the other of the first and second die packages.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Ping Ping Ooi, Kooi Chi Ooi, Shanggar Periaman