Abstract: A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Abstract: An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.

Abstract: The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor.

Abstract: A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.

Abstract: Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.

Abstract: An automated system for checking an integrated circuit cell layout includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comparing the cell layout to the reference cell layout to determine if a cell is of concern, and reporting the cell of concern to a user.

Abstract: SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A method for operating a static random access memory (SRAM) cell includes providing the SRAM cell having a static read margin and a static write margin, wherein the static read margin is greater than the static write margin; applying a dynamic power to perform a write operation on the SRAM cell; and applying a static power to perform a read operation on the SRAM cell.

Abstract: In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor.

Abstract: A method and system for verifying an integrated circuit design are provided. The method includes identifying cell tags embedded in a proposed integrated circuit design file, comparing cells identified as having a tag embedded therein to a cell library containing verified cell data to determine differences between the identified tagged cells and corresponding verified cell data from the cell library, and revising the proposed integrated circuit design to correct differences between the proposed integrated circuit design file and the verified cell data.

Abstract: This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line.

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Abstract: A pseudo 6T SRAM cell design comprising eight transistors is provided. An embodiment comprises a pair of cross-coupled inverters and a pair of pass-gate transistors electrically coupled to each inverter through the substrate. Each pass-gate transistor has a different beta ratio from the other transistor in its pair, and the smaller beta ratio in the pair acts as a “read” port while the larger beta ratio in the pair acts as a “write” port. Two pairs of bit lines are connected to the pass-gate transistors. A variety of word lines are connected to the pass-gate transistors. In one embodiment, a single word line is connected to all of the pass-gate transistors. In another embodiment, a pair of word lines is connected to the pass-gate transistors. In yet another embodiment, a different word line is connected to each pass-gate transistor.