Patents by Inventor Ping-Wei Wang

Ping-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287740
    Abstract: A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Wei-Cheng Wu, Hung-Jen Liao, Ping-Wei Wang, Wei Min Chan, Yen-Huei Chen
  • Patent number: 11121078
    Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Publication number: 20210280584
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • Publication number: 20210242222
    Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
  • Patent number: 11062963
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20210210389
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 8, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.
    Inventors: Wen-Chun KENG, Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
  • Patent number: 11056594
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 11043264
    Abstract: A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Publication number: 20210098468
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: January 29, 2020
    Publication date: April 1, 2021
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Publication number: 20210082475
    Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 10943827
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate. A top surface of the first fin structure is closer to the semiconductor substrate than a top surface of the second fin structure. The semiconductor device structure also includes a first epitaxial structure on the first fin structure. The semiconductor device structure further includes a second epitaxial structure on the third fin structure. The first epitaxial structure is wider than the second epitaxial structure.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chun Keng, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 10868019
    Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo, Ping-Wei Wang
  • Publication number: 20200335620
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 22, 2020
    Inventors: Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
  • Publication number: 20200335508
    Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Feng-Ming CHANG, Chia-Hao PAO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20200286550
    Abstract: A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Inventors: Wei-Cheng WU, Wei Min CHAN, Yen-Huei CHEN, Hung-Jen LIAO, Ping-Wei WANG
  • Publication number: 20200272781
    Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 27, 2020
    Inventors: Feng-Ming Chang, Ruey-Wen Chang, Ping-Wei Wang, Sheng-Hsiung Wang, Chi-Yu Lu
  • Publication number: 20200266200
    Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO, Ping-Wei WANG
  • Publication number: 20200266108
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate. A top surface of the first fin structure is closer to the semiconductor substrate than a top surface of the second fin structure. The semiconductor device structure also includes a first epitaxial structure on the first fin structure. The semiconductor device structure further includes a second epitaxial structure on the third fin structure. The first epitaxial structure is wider than the second epitaxial structure.
    Type: Application
    Filed: May 6, 2020
    Publication date: August 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Chun KENG, Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
  • Publication number: 20200251477
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20200251476
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: August 6, 2020
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien Jung Hung, Ping-Wei Wang