Patents by Inventor Ping-Wei Wang

Ping-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Shared bit lines for memory cells
    Patent number: 11552084
    Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim, Ruey-Wen Chang
  • Semiconductor Device With Leakage Current Suppression And Method Of Forming The Same
    Publication number: 20220416046
    Abstract: A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.
    Type: Application
    Filed: April 15, 2022
    Publication date: December 29, 2022
    Inventors: Shang-Rong Li, Shih-Hao Lin, Wen-Chun Keng, Chih-Chuan Yang, Chih-Hsiang Huang, Ping-Wei Wang
  • MEMORY DEVICE
    Publication number: 20220406372
    Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.
    Type: Application
    Filed: March 18, 2022
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao PAO, Kian-Long LIM, Chih-Chuan YANG, Jui-Wen CHANG, Chao-Yuan CHANG, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Four-poly-pitch SRAM cell with backside metal tracks
    Patent number: 11527539
    Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Feng-Ming Chang, Kian-Long Lim, Ping-Wei Wang, Lien Jung Hung, Ruey-Wen Chang
  • SRAM STRUCTURES
    Publication number: 20220383943
    Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
  • Source/Drain Feature Separation Structure
    Publication number: 20220367482
    Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
  • Semiconductor Memory Structure
    Publication number: 20220367488
    Abstract: A semiconductor device includes a program word line and a read word line over an active region. Each of the program word line and the read word line extends along a line direction. Moreover, the program word line engages a first transistor channel and the read word line engages a second transistor channel. The semiconductor device also includes a first metal line over and electrically connected to the program word line and a second metal line over and electrically connected to the read word line. The semiconductor device further includes a bit line over and electrically connected to the first active region. Additionally, the program word line has a first width along a channel direction perpendicular to the line direction; the read word line has a second width along the channel direction; and the first width is less than the second width.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Inventors: Hsin-Wen Su, Shih-Hao Lin, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang
  • Source/Drain Feature for Multigate Device Performance and Method of Fabricating Thereof
    Publication number: 20220367620
    Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.
    Type: Application
    Filed: December 15, 2021
    Publication date: November 17, 2022
    Inventors: Chih-Chuan Yang, Wen-Chun Keng, Chong-De Lien, Shih-Hao Lin, Hsin-Wen Su, Ping-Wei Wang
  • SEMICONDUCTOR DEVICE HAVING AN OFFSET SOURCE/DRAIN FEATURE AND METHOD OF FABRICATING THEREOF
    Publication number: 20220367483
    Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 17, 2022
    Inventors: Chih-Chuan YANG, Chia-Hao PAO, Wen-Chun KENG, Lien Jung HUNG, Ping-Wei WANG
  • WELL PICK-UP REGION DESIGN FOR IMPROVING MEMORY MACRO PERFORMANCE
    Publication number: 20220359536
    Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region, a WPU region, a first well extending lengthwise along a first direction through the circuit region and into the WPU region, a second well extending lengthwise along the first direction through the circuit region and into the WPU region, and a third well physically connecting a portion of the first well in the WPU region and a portion of the second well in the WPU region.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Chih-Chuan Yang, Chang-Ta Yang, Ping-Wei Wang
  • MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20220359538
    Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen SU, Chih-Chuan YANG, Shih-Hao LIN, Yu-Kuan LIN, Lien-Jung HUNG, Ping-Wei WANG
  • Structure and process of integrated circuit having latch-up suppression
    Patent number: 11495503
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • CONNECTION BETWEEN SOURCE/DRAIN AND GATE
    Publication number: 20220352181
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 3, 2022
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • BACKSIDE MEMORY INTEGRATION
    Publication number: 20220352256
    Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure according to the present disclosure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.
    Type: Application
    Filed: August 16, 2021
    Publication date: November 3, 2022
    Inventors: Hsin-Wen Su, Jui-Lin Chen, Shih-Hao Lin, Ming-Yen Chuang, Chenchen Jacob Wang, Lien-Jung Hung, Ping-Wei Wang
  • Multi-Gate Field-Effect Transistors and Methods of Forming the Same
    Publication number: 20220352334
    Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.
    Type: Application
    Filed: September 1, 2021
    Publication date: November 3, 2022
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Kuo-Hsiu Hsu, Shih-Hao Lin, Shang-Rong Li, Ping-Wei Wang
  • Tuning Gate Lengths In Multi-Gate Field Effect Transistors
    Publication number: 20220344484
    Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.
    Type: Application
    Filed: December 10, 2021
    Publication date: October 27, 2022
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chih-Hsuan Chen, Ping-Wei Wang
  • COMPACT ELECTRICAL CONNECTION THAT CAN BE USED TO FORM AN SRAM CELL AND METHOD OF MAKING THE SAME
    Publication number: 20220344353
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: July 8, 2022
    Publication date: October 27, 2022
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • CONTROLLING TRAP FORMATION TO IMPROVE MEMORY WINDOW IN ONE-TIME PROGRARM DEVICES
    Publication number: 20220336480
    Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
  • SRAM structures
    Patent number: 11475942
    Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
  • MAGNETIC DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    Publication number: 20220328561
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Application
    Filed: August 20, 2021
    Publication date: October 13, 2022
    Inventors: Jui-Lin CHEN, Chenchen Jacob WANG, Hsin-Wen SU, Ping-Wei WANG, Yuan-Hao CHANG, Po-Sheng LU, Shih-Hao LIN