Patents by Inventor Ping-Wei Wang

Ping-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM STRUCTURES
    Publication number: 20210398588
    Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.
    Type: Application
    Filed: January 21, 2021
    Publication date: December 23, 2021
    Inventors: Ping-Wei Wang, Chia-Hao Pao, Choh Fei Yeap, Yu-Kuan Lin, Kian-Long Lim
  • SRAM design with four-poly-pitch
    Patent number: 11205474
    Abstract: One aspect of this description relates to a memory cell including a first layer including a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure. The memory cell includes a second layer including a first active structure and a second active structure. The first gate structure overlaps the first active structure to form a first access transistor, the second gate structure overlaps the first active structure to form a first pull-down transistor, the third gate structure overlaps the first active structure to form a second pull-down transistor, and the fourth gate structure overlaps the first active structure to form a second access transistor. The second gate structure overlapping the second active structure to form a first pull-up transistor, the third gate structure overlapping the second active structure to form a second pull-up transistor.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Chuan Yang, Feng-Ming Chang, Kuo-Hsiu Hsu, Ping-Wei Wang
  • MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    Publication number: 20210391341
    Abstract: A memory device includes a substrate, first semiconductor layers and second semiconductor layers alternately stacked over the substrate, a first gate structure and a second gate structure crossing the first semiconductor layers and the second semiconductor layers, a first via and a second via over the first gate structure and the second gate structure, and a first word line and a second word line over the first via and the second via. Along a lengthwise direction of the first and second gate structures, a width of the first semiconductor layers is narrower than a width of the second semiconductor layers.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen SU, Yu-Kuan LIN, Shih-Hao LIN, Lien-Jung HUNG, Ping-Wei WANG
  • SRAM structure
    Patent number: 11201158
    Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien-Jung Hung, Ping-Wei Wang
  • Four-Poly-Pitch SRAM Cell with Backside Metal Tracks
    Publication number: 20210375883
    Abstract: A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Inventors: Kuo-Hsiu Hsu, Feng-Ming Chang, Kian-Long Lim, Ping-Wei Wang, Lien Jung Hung, Ruey-Wen Chang
  • Structure and Process of Integrated Circuit Having Latch-Up Suppression
    Publication number: 20210343601
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • SEMICONDUCTOR DEVICE HAVING FIN STRUCTURES
    Publication number: 20210343863
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first well region and a second well region and a first fin structure formed in a first region of the first well region. The semiconductor device structure also includes a second fin structure formed in a second region of the first well region. In addition, the second fin structure is narrower than the first fin structure. The semiconductor device structure also includes a third fin structure formed in a first region of the second well region. In addition, a sidewall of the first fin structure is substantially aligned with a sidewall of the third fin structure.
    Type: Application
    Filed: July 5, 2021
    Publication date: November 4, 2021
    Inventors: Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
  • STATIC RANDOM ACCESS MEMORY WITH MAGNETIC TUNNEL JUNCTION CELLS
    Publication number: 20210335797
    Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.
    Type: Application
    Filed: February 3, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ping-Wei Wang, Jui-Lin Chen, Yu-Kuan Lin
  • SHARED BIT LINES FOR MEMORY CELLS
    Publication number: 20210305262
    Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.
    Type: Application
    Filed: January 8, 2021
    Publication date: September 30, 2021
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim, Ruey-Wen Chang
  • Fin-based strap cell structure for improving memory performance
    Patent number: 11127746
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien Jung Hung, Ping-Wei Wang
  • STATIC RANDOM ACCESS MEMORY
    Publication number: 20210287740
    Abstract: A static random access memory (SRAM) includes a bit cell including a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a read multiplexer connected to the bit information path. The read multiplexer includes an n-type transistor configured to selectively couple the bit information path to a sense amplifier.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Wei-Cheng Wu, Hung-Jen Liao, Ping-Wei Wang, Wei Min Chan, Yen-Huei Chen
  • SRAM having irregularly shaped metal lines
    Patent number: 11121078
    Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY
    Publication number: 20210280584
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • CONTROLLING TRAP FORMATION TO IMPROVE MEMORY WINDOW IN ONE-TIME PROGRARM DEVICES
    Publication number: 20210242222
    Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
  • Structure and process of integrated circuit having latch-up suppression
    Patent number: 11062963
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • SEMICONDUCTOR DEVICE WITH FIN STRUCTURES
    Publication number: 20210210389
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.
    Type: Application
    Filed: March 8, 2021
    Publication date: July 8, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.
    Inventors: Wen-Chun KENG, Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
  • Semiconductor device having fin structures
    Patent number: 11056594
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Static random access memory method
    Patent number: 11043264
    Abstract: A method of performing a write operation on a static random access memory (SRAM) bit cell includes activating the bit cell by supplying a signal to a p-type pass gate of the bit cell, the signal causing the p-type pass gate to be in a conductive state, using a p-type transistor of a write multiplexer to maintain a data line at a logically high voltage, and transferring bit information from the data line to the activated bit cell using the p-type pass gate.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • Source/Drain Contact Having a Protruding Segment
    Publication number: 20210098468
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Application
    Filed: January 29, 2020
    Publication date: April 1, 2021
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • SRAM HAVING IRREGULARLY SHAPED METAL LINES
    Publication number: 20210082475
    Abstract: A semiconductor device includes a gate structure, a source/drain, a first via that is disposed over the gate structure and the source/drain, and a first metal line having a more elevated vertical position than the first via in a cross-sectional view. The first via is electrically coupled to both the gate structure and the source/drain. The first metal line and the first via each extends in a first direction. A first distance separates the metal line from the via in a second direction different from the first direction. The first metal line includes a protruding portion that protrudes outwardly in the second direction.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang