Patents by Inventor Pinghai Hao

Pinghai Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210159329
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
    Type: Application
    Filed: February 2, 2021
    Publication date: May 27, 2021
    Inventors: Dong Seup LEE, Jungwoo JOH, Pinghai HAO, Sameer PENDHARKAR
  • Patent number: 10964803
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 30, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 10861943
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 10714474
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Publication number: 20200185499
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Dong Seup LEE, Jungwoo JOH, Pinghai HAO, Sameer PENDHARKAR
  • Publication number: 20200161461
    Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Dong Seup LEE, Jungwoo JOH, Pinghai HAO, Sameer PENDHARKAR
  • Publication number: 20200064394
    Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.
    Type: Application
    Filed: May 1, 2019
    Publication date: February 27, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Dong Seup Lee, Jungwoo Joh, Pinghai Hao, Sameer Pendharkar
  • Patent number: 10312095
    Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 4, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Yoshikazu Kondo, Pinghai Hao, Sameer Pendharkar
  • Publication number: 20190157091
    Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.
    Type: Application
    Filed: October 18, 2018
    Publication date: May 23, 2019
    Inventors: Dong Seup LEE, Yoshikazu KONDO, Pinghai HAO, Sameer PENDHARKAR
  • Patent number: 10134596
    Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Yoshikazu Kondo, Pinghai Hao, Sameer Pendharkar
  • Patent number: 9865507
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9842895
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: December 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Fuchao Wang, Duofeng Yue
  • Publication number: 20170301673
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Patent number: 9741718
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Publication number: 20160322263
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9431302
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9412668
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Publication number: 20160197135
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Application
    Filed: February 29, 2016
    Publication date: July 7, 2016
    Inventors: Pinghai HAO, Fuchao WANG, Duofeng YUE
  • Patent number: 9305688
    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: PingHai Hao, Fuchao Wang, Duofeng Yue
  • Publication number: 20150325577
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs