Patents by Inventor Pinghai Hao

Pinghai Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7307309
    Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: December 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Jozef Mitros, Xiaoju Wu
  • Publication number: 20070218663
    Abstract: The invention provides, in one aspect, a method of fabricating a semiconductor device. This embodiment comprises depositing a gate layer over a gate dielectric layer located over a semiconductor substrate, and incorporating fluorine into the gate dielectric layer before doping the gate layer.
    Type: Application
    Filed: March 20, 2006
    Publication date: September 20, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Pinghai Hao, Imran Khan, Fan-Chi Hou
  • Patent number: 7268394
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Patent number: 7244651
    Abstract: The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the Vtp implant into a channel region of an n-well that substantially underlies a floating gate structure. The Vtp implant can be blocked by providing a mask overlying the surface of the channel region of the n-well during implantation of the Vtp implant.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Jozef Mitros, Pinghai Hao
  • Patent number: 7235451
    Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: June 26, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar
  • Patent number: 7208364
    Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Shanjen Pan, Sameer Pendharkar, Pinghai Hao, James R. Todd
  • Publication number: 20070080400
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 12, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharker, Pinghai Hao, Xiaoju Wu
  • Patent number: 7164160
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: January 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer P. Pendharker, Pinghai Hao, Xiaoju Wu
  • Publication number: 20060286741
    Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 21, 2006
    Inventors: Shanjen Pan, Sameer Pendharkar, Pinghai Hao, James Todd
  • Patent number: 7135373
    Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: November 14, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar
  • Patent number: 7122862
    Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar
  • Patent number: 7045418
    Abstract: The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 16, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Jozef Mitros, Weidong Tian, Pinghai Hao, Victor Ivanov
  • Patent number: 7018880
    Abstract: The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Larry B. Anderson, Fan Chi Hou, Xiaoju Wu, Yvonne Patton, Shanjen Pan, Zafar Imam
  • Patent number: 7005354
    Abstract: Depletion drain-extended MOS transistor devices and fabrication methods for making the same are provided, in which a compensated channel region is provided with p and n type dopants to facilitate depletion operation at Vgs=0, and an adjust region is implanted in the substrate proximate the channel side end of the thick gate dielectric structure for improved breakdown voltage rating. The compensated channel region is formed by overlapping implants for an n-well and a p-well, and the adjust region is formed using a Vt adjust implant with a mask exposing the adjust region.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: February 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Shanjen Pan, James R. Todd, Sameer Pendharkar, Tsutomu Kubota, Pinghai Hao
  • Publication number: 20050215018
    Abstract: A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shallow region therein. The first dopant penetrates the substrate to a depth that is less than the LDD junction depth. A second dopant is implanted into the substrate beyond the LDD junction depth to form a source/drain region. The implantation of the second dopant overpowers a substantial portion of the first dopant to define a floating ring in the LDD region that mitigates channel hot carrier effects.
    Type: Application
    Filed: May 24, 2005
    Publication date: September 29, 2005
    Inventors: Pinghai Hao, Shanjen Pan, Sameer Pendharkar
  • Publication number: 20050194631
    Abstract: A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity region. A first dielectric layer (360-364) is formed on an inner surface of the hole. A first electrode (306) is formed in the hole adjacent the dielectric layer.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 8, 2005
    Inventors: Pinghai Hao, Jozef Mitros, Xiaoju Wu
  • Publication number: 20050151171
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 14, 2005
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Publication number: 20050136579
    Abstract: The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
    Type: Application
    Filed: December 22, 2003
    Publication date: June 23, 2005
    Applicant: Texas Instruments, Incorporated
    Inventors: Pinghai Hao, Larry Anderson, Fan Chi Hou, Xiaoju Wu, Yvonne Patton, Shanjen Pan, Zafar Imam
  • Patent number: 6885054
    Abstract: The present invention provides a threshold voltage stabilizer for use with a MOS transistor having a body effect associated therewith. In one embodiment, the threshold voltage stabilizer, includes a body well located in a substrate, a source located in the body well, and a stabilization region positioned below the body well. The threshold voltage stabilizer is configured to provide a stabilization voltage to the stabilization region to increase a depletion region within the body well and thereby restrict the body effect to stabilize a threshold voltage of the MOS transistor.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: April 26, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Pinghai Hao, Imran M. Khan
  • Publication number: 20050067631
    Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.
    Type: Application
    Filed: September 29, 2003
    Publication date: March 31, 2005
    Inventors: Sameer Pendharker, Pinghai Hao, Xiaoju Wu