Patents by Inventor Po-Chun Lin

Po-Chun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11151597
    Abstract: The present disclosure provides a method, computer system and computer program product for determining interruption points based on emotion values in a content. According to the method, emotion values of one or more emotion catalogs at one or more time points of the content to be interrupted can be determined, and one or more interruption points can be determined based on the determined emotion values.
    Type: Grant
    Filed: January 5, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jen Ping Cheng, Chao Yuan Huang, Yen Lin Li, Lin Chung Liang, Po Chun Lin
  • Publication number: 20210280511
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210144107
    Abstract: Orchestrated chat services utilizing a centralized chat service with access to a plurality of chatbots registered to the chat service. User's seeking support from the orchestrated chat service interact with a single user interface, while the backend of the chat service extracts the intents and entities from the user's input into the chat service. The orchestrated chat service identifies one or more classifications of chatbots suitable for responding to the user's input within a prescribed level of confidence dictated by one or more orchestration rules and selects a chatbot predicted to most likely respond to the user's input in a correct and accurate manner. The orchestrated chat service formats the user input and chat history into format of the selected chatbot's API, forwards user input and history to the selected chatbot and returns the response from the selected chatbot to the user interface of the orchestrated chat service.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 13, 2021
    Inventors: Lin Chung Liang, Chao Yuan Huang, Jen Ping Cheng, Po-Chun Lin, Yen Lin Li
  • Patent number: 11004786
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20210098636
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Application
    Filed: January 20, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 10923455
    Abstract: The present disclosure is directed to a method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The method includes the steps of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: February 16, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10825794
    Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10811545
    Abstract: A sensing module including a sensing array, a first shielding layer, a second shielding layer, and a reflective layer is provided. The sensing array includes a plurality of light passing regions and a light receiving surface facing away from an object, and the sensing array is located between the first shielding layer having a plurality of first openings and the second shielding layer having a plurality of second openings. The second shielding layer is located between the sensing array and the reflective layer. The light beams reflected by the object sequentially pass through the first openings, the light passing regions, the second openings, and are then transmitted to the reflective layer. The light beams are reflected by the reflective layer and then pass through the second openings again to be transmitted to the light receiving surface of the sensing array. An image capturing apparatus is also provided.
    Type: Grant
    Filed: July 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Gingy Technology Inc.
    Inventors: Chiung-Han Wang, Wen-Chen Lee, Po-Chun Lin, Jen-Chieh Wu
  • Publication number: 20200294912
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20200266227
    Abstract: A sensing module including a sensing array, a first shielding layer, a second shielding layer, and a reflective layer is provided. The sensing array includes a plurality of light passing regions and a light receiving surface facing away from an object, and the sensing array is located between the first shielding layer having a plurality of first openings and the second shielding layer having a plurality of second openings. The second shielding layer is located between the sensing array and the reflective layer. The light beams reflected by the object sequentially pass through the first openings, the light passing regions, the second openings, and are then transmitted to the reflective layer. The light beams are reflected by the reflective layer and then pass through the second openings again to be transmitted to the light receiving surface of the sensing array. An image capturing apparatus is also provided.
    Type: Application
    Filed: July 14, 2019
    Publication date: August 20, 2020
    Applicant: Gingy Technology Inc.
    Inventors: Chiung-Han Wang, Wen-Chen Lee, Po-Chun Lin, Jen-Chieh Wu
  • Publication number: 20200143412
    Abstract: The present disclosure provides a method, computer system and computer program product for determining interruption points based on emotion values in a content. According to the method, emotion values of one or more emotion catalogs at one or more time points of the content to be interrupted can be determined, and one or more interruption points can be determined based on the determined emotion values.
    Type: Application
    Filed: January 5, 2020
    Publication date: May 7, 2020
    Inventors: Jen Ping Cheng, Chao Yuan Huang, Yen Lin Li, Lin Chung Liang, Po Chun Lin
  • Patent number: 10607858
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 31, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10580665
    Abstract: A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10566294
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 18, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10552862
    Abstract: The present disclosure provides a method, computer system and computer program product for determining interruption points based on emotion values in a content. According to the method, emotion values of one or more emotion catalogs at one or more time points of the content to be interrupted can be determined, and one or more interruption points can be determined based on the determined emotion values.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jacqueline Cheng, Chao Yuan Huang, Yen Lin Li, Lin Chung Liang, Po-Chun Lin
  • Patent number: 10535621
    Abstract: The present disclosure provides a method for preparing a semiconductor package. The method includes providing a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner. The method also includes forming a bump structure over the first upper surface, wherein the bump structure extends laterally across the first side of the first device.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: January 14, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 10446514
    Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 15, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu
  • Patent number: 10438887
    Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 8, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 10431559
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 1, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 10373932
    Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 6, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Po-Chun Lin, Chin-Lung Chu