Abstract: A semiconductor structure includes a first package including a substrate and a die disposed over the substrate and electrically connected to the substrate by a first conductive bump; a second package disposed over the first package and electrically connected to the substrate by a second conductive bump; and an adhesive disposed between the die and the second package.

Abstract: A semiconductor stacking structure is provided. The semiconductor stacking structure includes a substrate and at least one conductor. The substrate has at least one first through via formed at an edge of the substrate. The conductor is present in the first through via. At least one of the conductor and the first through via is exposed from the edge of the substrate.

Abstract: A semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (RDL) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. The molding member does not extend into an interface between the first semiconductor device and the second semiconductor device.

Abstract: A semiconductor package includes a first device; a second device laterally adjacent to the first device; a molding member encapsulating the first device and the second device; and a lateral bump structure implementing a lateral signal path between the first device and the second device. A portion of the molding member is disposed between the first device and the second device.

Abstract: A semiconductor structure includes a substrate including a first side and a second side opposite to the first side; a first via extending through the substrate; a second via extending through the substrate; and a metallic structure disposed between the first via and the second via, wherein the first via is isolated from the second via by the metallic structure, the first via and the second via are configured to connect to a signal source or transmit a signal, and the metallic structure is configured to connect to a power or a ground.

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. The top interposer is electrically connected to the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are present between the package substrate and the top interposer.

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

Abstract: A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.

Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. The top interposer is electrically connected to the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are present between the package substrate and the top interposer.

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

Abstract: A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

Abstract: A semiconductor structure includes a substrate; a chip disposed over the substrate; and a molding disposed over the substrate and surrounding the chip at a molding temperature. The warpage of the substrate is convex or about zero at the molding temperature or 10° C. more or less than the molding temperature.

Abstract: A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second surface opposite thereto; a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface; a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars; and a first redistribution layer disposed on the second surface of the first interposer. The first surface has a clearance region where is free of the first bumps. A first chip is disposed over the first redistribution layer. The first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface. A plurality of second bumps interconnecting the first redistribution layer with the first chip.

Abstract: A package structure includes a substrate, an interconnection unit, and an optical unit. The substrate has a surface. The interconnection unit is disposed on the substrate and includes a reflective bump, in which reflective bump is disposed on the surface of the substrate and has an opening therein. The optical unit is joined with the surface of the substrate and configured to receive a light beam from the interconnection unit, in which a vertical projection of the optical unit on the substrate is present within a vertical projection of the opening of the reflective bump on the substrate.

Abstract: An electronic structure is provided. The electronic structure includes a first board structure, a first contact pad, a first joint member, and a second joint member. The first contact pad is disposed on the first board structure. The first joint member is disposed on the first contact pad, in which the first joint member has a first Young's modulus. The second joint member is disposed on the first joint member, in which the second Young's modulus has a second Young's modulus, and the second Young's modulus is greater than the first Young's modulus.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a chip disposed over the substrate; disposing the substrate over a first molding member; disposing a second molding member over the substrate to encapsulate the chip; disposing a molding material around the chip; forming a molding over the substrate and around the chip; removing the first molding member; removing the second molding member; wherein the first molding member includes a curved surface protruded towards the substrate, the chip or the second molding member.

Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.