Abstract: A method of manufacturing a semiconductor structure includes providing a substrate and a chip disposed over the substrate; disposing the substrate over a first molding member; disposing a second molding member over the substrate to encapsulate the chip; disposing a molding material around the chip; forming a molding over the substrate and around the chip; removing the first molding member; removing the second molding member; wherein the first molding member includes a curved surface protruded towards the substrate, the chip or the second molding member.

Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

Abstract: A semiconductor package includes a semiconductor chip, an interposer, a first redistribution layer, and a molding compound. The semiconductor chip has a first surface and a second surface opposite to the first surface and at least one sidewall connected to the first surface and the second surface. The interposer is present on the first surface of the semiconductor chip. The first redistribution layer is present on the second surface of the semiconductor chip and is electrically connected to the semiconductor chip. The molding compound is present between the interposer and the first redistribution layer and is connected to the sidewall of the semiconductor chip.

Abstract: A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one active region and at least one gap region surrounded the active region, the flow hindering supporter is located on the gap region; subsequently, disposing at least one die structure onto the active region of the substrate respectively; and then injecting a molding compound flowed into the gap region, to mold the flow hindering supporter and the die structure with the molding compound.

Abstract: A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical bump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

Abstract: A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first surface towards the second surface; a conductive layer disposed over the first surface and within the recess; and a passivation disposed over the first surface and partially covering the conductive layer, wherein the conductive layer disposed within the recess is exposed from the passivation.

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

Abstract: The present disclosure provides a semiconductor apparatus having a plurality of semiconductor dies stacked in a face-to-face manner and a method for preparing the same. By stacking dies having different functions vertically in a face-to-face manner, a face-to-face communication is implemented between the dies having different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor apparatus, as compared to a semiconductor apparatus with dies having different functions arranged in a laterally adjacent manner. Furthermore, the signal path of the dies having different functions vertically stacked in the face-to-face manner is shorter than the signal path of the dies having different functions arranged in a laterally adjacent manner; consequently, the dies having different functions vertically stacked in the face-to-face manner of the present disclosure can be applied to high-speed electronic devices.

Abstract: A carbon fiber washer is provided and includes a carbon fiber fabric made of a plurality of fiber bundles being woven, in which each of the plurality of fiber bundles is made of discontinuous fibers; the advantage of the carbon fiber washer of the present invention includes high temperature and fatigue resisting, and weather proofing. The structure of the carbon fiber washer is stable due to the use of discontinuous fibers; breakages of discontinuous fibers do not affect other unbroken discontinuous fibers, so that the structure of the carbon fiber washer would not be loosened or delaminated and the service life can be prolonged accordingly.

Abstract: One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least one conductive terminal disposed on the integrated circuit die, a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal, and at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at least one conductive terminal.

Abstract: A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.

Abstract: A semiconductor chip includes a semiconductor device with an upper surface and a lower surface opposite to the upper surface. The semiconductor device includes an input terminal, a plurality of through silicon vias, a plurality of selection pads, a plurality of tilt pads and a plurality of tilt conductive structures. The through silicon vias are extended through the semiconductor device. The selection pads are located on the lower surface The tilt pads are located on the upper surface and connected to the selection pads through the through silicon vias respectively. Each tilt pad includes a pad surface that is non-parallel to the upper surface. A lower end of each tilt conductive structure is in contact with the pad surface of each tilt pad, and an upper end of each tilt conductive structure is vertically overlapped with an immediately-adjacent one of the tilt pads.

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; a pad disposed over the first surface; a first passivation disposed over the first surface and partially covering the pad; a redistribution layer (RDL) disposed over the first passivation, and including a conductive line extending over the first passivation and a second passivation partially covering the conductive line. The conductive line includes a via portion coupled with the pad and extended within the first passivation towards the pad, and a land portion extended over the first passivation, wherein the land portion includes a plurality of first protrusions protruded away from the first passivation.

Abstract: A conductive connection structure includes a semiconductor substrate, a conductive pillar, and a stress buffer layer. The conductive pillar is in the semiconductor substrate. The stress buffer layer is between the semiconductor substrate and the conductive pillar. The conductive pillar has a protruding portion penetrating through the stress buffer layer.

Abstract: One aspect of the present disclosure provides a semiconductor device. In some embodiments, the semiconductor device includes an integrated circuit die, at least one conductive terminal disposed on the integrated circuit die, a frame positioned on the integrated circuit die, wherein the frame substantially exposes the at least one conductive terminal, and at least one conductive bump positioned in the frame, wherein the at least one conductive bump electrically connects the at least one conductive terminal.

Abstract: A method of manufacturing chips from a semiconductor wafer having a plurality of streets on a front surface of the semiconductor wafer is provided. The method includes: forming a plurality of crack stopping structures on the semiconductor wafer at locations respectively aligned with intersections of the streets; irradiating a laser beam focused inside the semiconductor wafer along the streets to induce cracks; and breaking the irradiated semiconductor wafer along the cracks to the crack stopping structures, so as to separate the irradiated semiconductor wafer into the chips.

Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a non-through plug extending from the first side to an internal plane of the semiconductor substrate without extending through the second side.