Abstract: A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion.

Abstract: A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first insulation layer; a buffering member embedded into the first insulation layer; a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member.

Abstract: A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.

Abstract: A carbon fiber washer is provided and includes a carbon fiber fabric made of a plurality of fiber bundles being woven, in which each of the plurality of fiber bundles is made of discontinuous fibers; the advantage of the carbon fiber washer of the present invention includes high temperature and fatigue resisting, and weather proofing. The structure of the carbon fiber washer is stable due to the use of discontinuous fibers; breakages of discontinuous fibers do not affect other unbroken discontinuous fibers, so that the structure of the carbon fiber washer would not be loosened or delaminated and the service life can be prolonged accordingly.

Abstract: A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.

Abstract: A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.

Abstract: A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion.

Abstract: One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes an electronic component and a board structure. The board structure includes a dielectric layer structure and at least one elastomer. The dielectric layer structure has a mount region and a peripheral region surrounding the mount region. The electronic component is disposed on the mount region, and the peripheral region has at least one first through hole. The elastomer is disposed in the first through hole.

Abstract: A semiconductor structure includes a substrate; a pad disposed over the substrate; a passivation disposed over the substrate and exposing a portion of the pad; and a bump disposed over the portion of the pad. The bump includes a buffering member disposed over the portion of the pad; and a conductive layer surrounding the buffering member and electrically connected to the pad.

Abstract: A waveguide including a substrate, a plurality of cladding layers, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The cladding layers are present on the substrate and define at least one tunnel therein, in which at least one of the cladding layers is made of metal. The first dielectric layer is disposed in the tunnel and has a first refractive index N1. The second dielectric layer is disposed in the tunnel and has a second refractive index N2. The third dielectric layer is disposed in the tunnel and has a third refractive index N3, and N2>N1 and N2>N3, in which the second dielectric layer is present between the first and third dielectric layers.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is foamed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad. A package structure using the wire bonding method is also provided.

Abstract: A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

Abstract: A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.

Abstract: A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections.