Abstract: A semiconductor device includes a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further includes a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

Abstract: A mobile Device, service device, and service request processing methods thereof are described. The service request processing method is adopted by a service device, includes: establishing, by a touch panel of the service device, a communication channel to a mobile device; receiving, by the touch panel, a service request sent from the mobile device via the communication channel; generating service information according to the service request; and transmitting the service information to the mobile device via the communication channel.

Abstract: An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above the substrate. The conductive pillar is disposed in the via. The connecting structure is at least partially disposed in the via and connecting the conductive pillar and the metal layer. At least a first portion of the connecting structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal expansion of the conductive pillar. A projection of the transistor in the via overlaps with the connecting structure.

Abstract: A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections.

Abstract: An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above the substrate. The conductive pillar is disposed in the via. The connecting structure is at least partially disposed in the via and connecting the conductive pillar and the metal layer. At least a first portion of the connecting structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal expansion of the conductive pillar. A projection of the transistor in the via overlaps with the connecting structure.

Abstract: A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further comprises a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions.

Abstract: A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base.

Abstract: A through silicon via (TSV) stacked structure made of stacked substrates. Each substrate includes multiple tapered through silicon vias, wherein the wider end of each tapered through silicon via is provided with a recessed portion and the narrower end of each tapered through silicon via protrudes from the substrate. The substrates are stacked one after another with the narrower end of each tapered through silicon via being fitting and jointing into a corresponding recessed portion of the tapered through silicon via.

Abstract: A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base.

Abstract: A semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface. A semiconductor device is mounted on the first surface. A mold cap encapsulates the semiconductor device. The mold cap includes a vertical extension portion covering the sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface.