Abstract: An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.

Abstract: The present invention discloses a packaging structure of a light-sensing element with reduced packaging area, wherein the central line of the light-sensing element coincides with the central line of the substrate in order to save the area expended in the conventional technology owing to that the central line of the light-sensing region coincides with the central line of the substrate. Thereby, the overall packaging area is effectively reduced. Further, engagement portions are formed in appropriate positions, which can be used to position the lens base and the lens cone installed subsequently in order to align them to the central line of the light-sensing region.

Abstract: The present invention discloses a packaging method of a light-sensing semiconductor device and a packaging structure thereof, wherein a matrix of spacer walls is formed on a light-sensing wafer, which has multiple light-sensing chips, and the adhesive is directly applied to between two neighboring spacer walls on the non-light-sensing regions. Thus, when the light transparent cover is installed, there is no more adhesive dropping onto the light-sensing regions of the light-sensing chips. Further, when the light transparent cover is pressed to join with the spacer walls, with the trenches formed at the tops of the spacer walls, the adhesive will not overflow from the joint seams into the light-sensing regions.

Abstract: An image sensing device package structure is formed by using a base and a light transparent layer to package an image sensing device. The image sensing device is electrically connected to metallization traces on the base by means of wire bonding. Through change of the positions of the metallization traces, contacts between bonding wires and the metallization traces are made slightly higher than the top of the image sensing device, thereby shortening the wire bonding pitch of the bonding wires and thus reducing the package area.

Abstract: An image sensor package structure is proposed, in which the electric connection of an image sensing chip and the assembly of a housing and a lens barrel are separately carried out to avoid restriction in the packaging process and influence of outside contaminants. Moreover, corresponding faces of the housing and the lens barrel are designed to be smooth surfaces to reduce the probability of adhesion and accumulation of outside contaminants, thereby enhancing the process yield and also reducing the process cost.

Abstract: The present invention discloses a packaging structure of a light-sensing device with a spacer wall, wherein a spacer wall is used to protect the light-sensing region from external pollutants or two spacer walls are used to confine the glue to therebetween lest the overflow glue pollute the light-sensing region as in the conventional technology. Further, the present invention can reduce the packaging area and can promote the yield and quality obviously.

Abstract: A packaging structure of a light sensation module includes a substrate, a light sensation chip, a housing and a lens barrel. The light sensation chip is installed on the substrate and is electrically connected to the substrate. The lens barrel is movably installed to the housing, and the corresponding surfaces of the housing and the lens barrel are smooth. Thereby, the pollutants brought about by friction can be reduced; the deposition of external pollutants can be avoided; the yield can be promoted; and the cost can be lowered.

Abstract: The present invention relates to a package structure for an optical sensor having a base set with the plurality of metallization traces on its upper and under surface and several conductors passing through the base electrically connects to the plurality of metallization traces on the surface; at least one optical sensor and its peripheral frame are set upon the base in which the conductors can be located within the frame area or the area between the optical sensor and the frame; and a light-pervious lid encapsulates the frame and completes the package structure. In addition, an enclosing base having a containing capacity can be adopted to replace the base and the frame. The present invention can efficiently raise the reliability of elements and yield and quality by said package structure.

Abstract: In an image sensing chip package structure, plated through vias penetrate a substrate to electrically connect metallization traces disposed on the upper and lower surfaces of the substrate. The plated through vias can be opened from the center of the substrate instead of being located at the periphery of the substrate. Contamination can thus be avoided during the glue dispensing process, and protection layers can also be used to seal gaps generated by the plated through vias, hence enhancing the producing yield. Moreover, protection layers having stickiness can further be used to secure components so as to reduce the production cost and enhance the product quality.

Abstract: The present invention discloses a packaging structure of a light-sensing element and a fabrication method thereof, wherein the light-sensing chip is installed on the substrate, and then a cleaning step is undertaken; next, a light transparent cover with a cavity is installed to the substrate with a glue material in order to envelop the light-sensing chip. Thereby, the present invention not only can clean pollutants completely and promote the yield, but also can reduce the packaging area. In the present invention, the engagement portions may also be formed on the substrate and the light transparent cover so that the alignment can be undertaken easily.

Abstract: A sand blasting machine consists of a working chest and an air compressor that are coupled together. The working chest includes a casing, a upper lid, a nozzle holding dock, a nozzle, an air discharge filter device, an actuation switch, a left glove operation means and a right glove operation means. The air compressor includes an air compressor body, a return tube and a foot frog. By means of these elements, the air compressor and the working chest are coupled together in an integrated manner. Hence carrying and transportation are easier. Sand blasting operation can be performed flexibly without site constraint.

Abstract: The invention discloses an extension box of storage media, which mainly utilized a plurality of heat dissipation fins protruding from a bottom surface of a bottom shell of the extension box. The heat dissipation fins efficaciously dissipate heat from the storage media, so it improves the dissipation heat efficiency and reduces breakdown for the storage media. The extension box of storage media of the present invention is electrically connected with an external electronic apparatus by a universal series bus (USB) or an IEEE 1394 interface connector for transmitting a data.

Abstract: A method and a device for detecting a preamble type of a wireless data frame are provided The preamble has a synchronization (SYNC) field and a start frame delimiter (SFD) field, and the method comprises following steps. The wireless data frame is first received, and then determined whether the wireless data frame has a short preamble. When the wireless data frame has the short preamble, the wireless data frame is transmitted to a MAC device. In addition, if the wireless data frame does not have the short preamble, it determines whether the wireless data frame has a long preamble. When the wireless data frame has the long preamble, the wireless data frame is then transmitted to the MAC device.

Abstract: A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width.

Abstract: A method of forming a triple well structure. A first photoresist layer is formed on a substrate having a first conductive type. A first ion implantation process is performed to form a first well, which has the first conductive type but a dopant concentration of the first well is higher than a dopant concentration of the substrate. The first photoresist layer is baked. A second ion implantation process is performed through the baked first photoresist layer to form a first doped region under the first well. The first doped region has a second conductive type. After removing the first photoresist layer, a second photoresist layer is formed on the substrate. A third ion implantation process is performed to form a second doped region in the substrate around the first well and to form a second well in the substrate. The second doped region and the second well have the second conductive type. The second doped region and the first doped region together surround the first well.

Abstract: In this invention a global row redundancy scheme for a DRAM is described which effectively uses the resources of the chip to produce an area efficient design. The DRAM is constructed from two types of memory blocks, one that has a redundant cell array and one that does not. Both memory block types contain a memory cell array and bit line sense amplifiers. The bit line sense amplifiers, contained on the block with the redundant cell array, are shared with the memory cell array also contained in the block, and thus eliminating the need for sense amplifiers for use only with the redundant cell array. Although, every block could contain a redundant cell array, only one or two blocks with the redundant cell array are normally used.

Abstract: A vacuum thermal cooker comprising an outer cooler, an inner cooker, a sealing lid unit and an insulating disc, the inner cooker being used for boiling food and then to be placed in the outer cooker sealed by the sealing lid unit and then the air in the outer cooker being sucked out by a separate simple sucking pump operated by hand, the interior of the outer cooker becoming vacuum so that the heat of the food and the inner cooker may be kept for a long period of time, not easily cooled off by function of the vacuum condition of the outer cooker.