Abstract: A multiple output rectifier includes a comparator-based active rectification circuit and a controller, wherein the controller is coupled to the comparator-based active rectification circuit. The comparator-based active rectification circuit is used for generating and outputting each output voltage of a plurality of output voltages according to an input voltage, the each output voltage, and a control signal corresponding to the each output voltage. The controller is used for generating the control signal according to the each output voltage and a reference voltage corresponding to the each output voltage.

Abstract: A single-inductor multiple-output (SIMO) power converter converts an input voltage into an output voltage and a biasing voltage. The SIMO power converter comprises an inductor and a primary power switch, and a control circuit. The inductor is configured for storing energy from the input voltage. The primary power switch has a control node and is connected between the inductor and the output voltage which powers an output load. The control circuit controls the primary power switch comprising an auxiliary power switch and a driver. The auxiliary power switch is connected between the inductor and the biasing voltage. The driver, powered by the biasing voltage, drives the control node. The biasing voltage determines a signal level at the control node. The primary power switch and the auxiliary power switch are controlled to distribute the energy stored in the inductor to the output voltage and the biasing voltage.

Abstract: A connector with latch protection includes a metal casing, an insulating body, plural metal terminals and a partition. The insulating body covers the interior of the metal casing and has a tab extended forwardly from the front of the insulating body and disposed apart on the top and bottom of the tab respectively, and both sides of the tab corresponding to a connecting plug form an inwardly concave portion, and both sides of the partition have a protection plate corresponding to each inwardly concave portion and the front of the tab and bent and extended forwardly. When the partition is embedded into the insulating body by a molding method, a portion of the two metal protection plates exposed from the tab forms a pair of latch grooves for latching the connecting plug to effectively improve the durability and life and lower the manufacturing cost of the connector significantly.

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.

Abstract: A connector with latch protection includes a metal casing, an insulating body, plural metal terminals and a partition. The insulating body covers the interior of the metal casing and has a tab extended forwardly from the front of the insulating body and disposed apart on the top and bottom of the tab respectively, and both sides of the tab corresponding to a connecting plug form an inwardly concave portion, and both sides of the partition have a protection plate corresponding to each inwardly concave portion and the front of the tab and bent and extended forwardly. When the partition is embedded into the insulating body by a molding method, a portion of the two metal protection plates exposed from the tab forms a pair of latch grooves for latching the connecting plug to effectively improve the durability and life and lower the manufacturing cost of the connector significantly.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A multiple output rectifier includes a comparator-based active rectification circuit and a controller, wherein the controller is coupled to the comparator-based active rectification circuit. The comparator-based active rectification circuit is used for generating and outputting each output voltage of a plurality of output voltages according to an input voltage, the each output voltage, and a control signal corresponding to the each output voltage. The controller is used for generating the control signal according to the each output voltage and a reference voltage corresponding to the each output voltage.

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.

Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.

Abstract: A bit cell includes a program device comprising a first source/drain region and a second source/drain region separated by a first channel. The first source/drain region, the second source/drain region, and the first channel are positioned along a first direction. The bit cell also includes an electrical fuse (eFuse) having a conduction path along the first direction. A conductive element is electrically connected with the first source/drain region and one end of the eFuse.

Abstract: A method for automatically generating an image description includes following steps of: obtaining a first image data; analyzing a text file corresponding to the first image data; calculating occurrences and distribution ratios of terms, each of which contains a target word, from the text file, so as to obtain a plurality of the terms having the distribution ratios greater than a threshold; comparing the distribution ratios of the terms so as to find out at least one key term; finding out one of a plurality of lexical chains containing the key term with a greatest distribution ratio so as to generate a narrative language chain; and setting the narrative language chain as a description of the first image data. A system for automatically generating an image description and a non-volatile computer-readable storage media are also disclosed.

Abstract: A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Abstract: A display module includes a panel frame, a display panel, a system frame, and a printed circuit board. The panel frame includes a baseplate having at least one edge, at least one sidewall located on the edge, at least one top wall adjacent to the sidewall, and a support element. An accommodating space is formed by the sidewall and the baseplate. The support element includes a first support portion and a second support portion connected to the first support portion. The support element extends from the edge of the baseplate toward the outside of the accommodating space. The display panel is disposed on the panel frame. The first support portion is disposed on the system frame. The printed circuit board is disposed on the second support portion.

Abstract: A method for automatically generating an image description includes following steps of: obtaining a first image data; analyzing a text file corresponding to the first image data; calculating occurrences and distribution ratios of terms, each of which contains a target word, from the text file, so as to obtain a plurality of the terms having the distribution ratios greater than a threshold; comparing the distribution ratios of the terms so as to find out at least one key term; finding out one of a plurality of lexical chains containing the key term with a greatest distribution ratio so as to generate a narrative language chain; and setting the narrative language chain as a description of the first image data. A system for automatically generating an image description and a non-volatile computer-readable storage media are also disclosed.

Abstract: A signal interconnect includes a transmission line, a termination circuit coupled to the transmission line, and a high pass filter circuit coupled in series along the transmission line. The high pass filter circuit includes a first resistive circuit and a first capacitive circuit coupled in parallel. The first resistive circuit has a resistance based on a difference between a resistance of the transmission line at a high frequency and a resistance of the transmission line at a low frequency.

Abstract: Methods and an apparatus related to generating parameters and guidelines used in the manufacture of semiconductor IC devices are described. A method includes measuring a first oscillating signal produced by a first ring oscillator that includes a first interconnect provided in a first interconnect layer of an IC, selecting a first mode of operation for a second ring oscillator circuit that includes a second interconnect disposed in alignment with the first interconnect, selecting a second mode of operation for the second ring oscillator circuit, and determining one or more characteristics of the first interconnect based on a difference in frequency of the first oscillating signal produced when the second ring oscillator circuit is operated in the first mode and frequency of the first oscillating signal when the second ring oscillator circuit is operated in the second mode.

Abstract: A safety clamp system for an emergency start of a vehicle battery comprises a boost circuit, a voltage-stabilizing circuit, a control unit, a power detection circuit, a battery-clamp-loose detection circuit, an alarm circuit, an auto-detect-battery-voltage-and-short-circuit detection circuit, a driving circuit and a turn-on/off detection circuit. The power detection circuit and the auto-detect-battery-voltage-and-short-circuit detection circuit detect whether an input voltage or the vehicle battery is normal or abnormal. If normal, the control unit controls the driving circuit to drive the turn-on/off detection circuit, so that a power supplied by an external lithium battery is sent to the vehicle battery. If abnormal, abnormal detection signals are sent to the control unit to drive the alarm circuit. If a battery clamp is loose, the control unit controls the driving circuit to stop driving the turn-on/off detection circuit, so that the power is not sent to the vehicle battery.