Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A temperature measuring device includes a device main body, a signal control module, a movable shutter module, and a first and a second non-contacting temperature sensing module. The movable shutter module includes an electric control driver, a movable shutter structure, and an electric control heater, and the movable shutter structure includes a black substance for generating a predetermined heating temperature from being heated by the electric control heater. The first non-contacting temperature sensing module is configured for measuring an object temperature of an object so as to obtain object temperature information of the object. The second non-contacting temperature sensing module is configured for measuring the predetermined heating temperature generated by the black substance of the movable shutter structure so as to obtain black body temperature information of the black substance.

Abstract: A single inductor multiple output regulator includes an inductor, a number of capacitors, a number of switches coupled with the capacitors and a control circuit coupled with the switches and configured to apply at least two multi-switching pulses to a multi-pulse controlled one of the switches in each cycle.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: A temperature calibration method includes providing a temperature measuring device including a movable shutter module, and a first and a second non-contacting temperature sensing module, and a movable shutter structure of the movable shutter module includes a black substance for generating a predetermined heating temperature; moving the movable shutter structure to a first position by driving of the electric control driver, so as to completely block a first temperature-measuring viewing angle of the first non-contacting temperature sensing module and a second temperature-measuring viewing angle of the second non-contacting temperature sensing module by the black substance; measuring the predetermined heating temperature that is generated by the black substance by the second non-contacting temperature sensing module at the second temperature-measuring viewing angle so as to obtain black body temperature information of the black substance; and calibrating the first non-contacting temperature sensing module acco

Abstract: A method of forming semiconductor structure includes forming a bit line structure on a substrate, forming a first landing pad material lower than the bit line structure between two adjacent bit line structures, shaping a top surface of the bit line structure to form an edge area of the top surface lower than a center area of the top surface, forming a second landing pad material on the bit line structure and the first landing pad material, and removing at least a portion of the second landing pad material to form a landing pad.

Abstract: A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber, a hot plate disposed in the baking chamber, and a cover plate disposed over the hot plate. The cover plate has a plurality of exhaust holes. The exhaust holes include a first exhaust hole and a second exhaust hole arranged in a first direction. The first exhaust hole and the second exhaust hole have different sizes.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

Abstract: A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber having an exhaust port on a sidewall of the baking chamber, a hot plate disposed in the baking chamber, an exhaust line coupled to the exhaust port, and a cover plate disposed over the hot plate and between the hot plate and the exhaust port. The exhaust line is configured to exhaust out an atmosphere inside the baking chamber in an exhaust direction. The cover plate has a plurality of exhaust holes to allow air to flow through. The exhaust holes include a first exhaust hole and a second exhaust hole arranged in a first direction that is perpendicular to the exhaust direction.

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber having an exhaust port on a sidewall of the baking chamber, a hot plate disposed in the baking chamber, an exhaust line coupled to the exhaust port, and a cover plate disposed over the hot plate and between the hot plate and the exhaust port. The exhaust line is configured to exhaust out an atmosphere inside the baking chamber in an exhaust direction. The cover plate has a plurality of exhaust holes to allow air to flow through. The exhaust holes include a first exhaust hole and a second exhaust hole arranged in a first direction that is perpendicular to the exhaust direction.

Abstract: A photoresist baking apparatus is provided. The photoresist baking apparatus includes a baking chamber, a hot plate, an exhaust line, and a cover plate. The baking chamber has an exhaust port on a sidewall thereof. The hot plate is disposed in the baking chamber and is configured to support a wafer and heat a photoresist material over the wafer. The exhaust line is coupled to the exhaust port and is configured to exhaust out the atmosphere inside the baking chamber. The cover plate is disposed over the hot plate and between the hot plate and the exhaust port. The cover plate has multiple exhaust holes to allow air to flow through. The size of one of the exhaust holes farther from the exhaust port is larger than the size of one of the exhaust holes closer to the exhaust port.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A temperature measuring device includes: a carrier, a temperature measuring module and a limiting member. The carrier includes a case body, a substrate disposed on the case body, a slot disposed on the case body, a first hole disposed on the case body, and a second hole. The first hole and the second hole are in communication with each other to form a gas flow path. The temperature measuring module includes a temperature measuring unit. The temperature measuring unit is disposed on the substrate, and the temperature measuring unit corresponds to the first hole. The limiting member is disposed on the carrier. The limiting member includes a positioning structure disposed on the slot and a limiting structure connected to the positioning structure.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A multiple output rectifier includes a comparator-based active rectification circuit and a controller, wherein the controller is coupled to the comparator-based active rectification circuit. The comparator-based active rectification circuit is used for generating and outputting each output voltage of a plurality of output voltages according to an input voltage, the each output voltage, and a control signal corresponding to the each output voltage. The controller is used for generating the control signal according to the each output voltage and a reference voltage corresponding to the each output voltage.

Abstract: A single-inductor multiple-output (SIMO) power converter converts an input voltage into an output voltage and a biasing voltage. The SIMO power converter comprises an inductor and a primary power switch, and a control circuit. The inductor is configured for storing energy from the input voltage. The primary power switch has a control node and is connected between the inductor and the output voltage which powers an output load. The control circuit controls the primary power switch comprising an auxiliary power switch and a driver. The auxiliary power switch is connected between the inductor and the biasing voltage. The driver, powered by the biasing voltage, drives the control node. The biasing voltage determines a signal level at the control node. The primary power switch and the auxiliary power switch are controlled to distribute the energy stored in the inductor to the output voltage and the biasing voltage.