Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804382
    Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 13, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Ando, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10804278
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Publication number: 20200321394
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Pouya Hashemi, Bruce B. Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Publication number: 20200312722
    Abstract: A method for fabricating a semiconductor device including vertical transistors having uniform channel length includes defining a channel length of at least one first fin formed on a substrate in a first device region and a channel length of at least one second fin formed on the substrate in a second device region. Defining the channel lengths includes creating at least one divot in the second device region. The method further includes modifying the channel length of the at least one second fin to be substantially similar to the channel length of the at least one first fin by filling the at least one divot with additional gate conductor material.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Alexander Reznicek, Pouya Hashemi
  • Patent number: 10790001
    Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pouya Hashemi, Nathan Philip Marchack
  • Patent number: 10790357
    Abstract: Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Patent number: 10784347
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau
  • Publication number: 20200295256
    Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Inventors: Pouya Hashemi, Takashi Ando, Dimitri Houssameddine, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee
  • Publication number: 20200286995
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 10770652
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The method first provides an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a first conductive layer on top the MTJ cap layer and a second conductive metal layer formed on top the first conductive layer. A pillar mask structure is then patterned and formed on the second conductive layer. The resulting structure is subject to lithographic patterning and etching to form a patterned bilayer metal hardmask pillar structure on top the MTJ cap layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned bilayer metal hardmask pillar.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Patent number: 10770461
    Abstract: A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • Publication number: 20200279777
    Abstract: I/O devices for gate-all-around transistors are provided. In one aspect, a method of forming an integrated circuit includes: forming at least first/second logic and I/O device stacks on a wafer having nanosheets of a channel material; forming an IL oxide on the nanosheets in the first and second device stacks; depositing a gate dielectric on the nanosheets in the first and second device stacks; selectively forming an oxygen containing layer on the second device stack; depositing a sacrificial layer onto the nanosheets and onto the oxygen containing layer; depositing a barrier layer onto the first and second device stacks; annealing the first and second device stacks to drive oxygen atoms from the oxygen containing layer into the IL oxide in the second device stack; removing the oxygen containing layer, sacrificial layer and barrier layer; and depositing a conformal gate conductor over the gate dielectric. An integrated circuit is also provided.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi
  • Patent number: 10763177
    Abstract: I/O devices for gate-all-around transistors are provided. In one aspect, a method of forming an integrated circuit includes: forming at least first/second logic and I/O device stacks on a wafer having nanosheets of a channel material; forming an IL oxide on the nanosheets in the first and second device stacks; depositing a gate dielectric on the nanosheets in the first and second device stacks; selectively forming an oxygen containing layer on the second device stack; depositing a sacrificial layer onto the nanosheets and onto the oxygen containing layer; depositing a barrier layer onto the first and second device stacks; annealing the first and second device stacks to drive oxygen atoms from the oxygen containing layer into the IL oxide in the second device stack; removing the oxygen containing layer, sacrificial layer and barrier layer; and depositing a conformal gate conductor over the gate dielectric. An integrated circuit is also provided.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi
  • Publication number: 20200273710
    Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Jingyun Zhang, Choonghyun Lee, Takashi Ando, Alexander Reznicek, Pouya Hashemi
  • Patent number: 10756176
    Abstract: A stacked nanosheet semiconductor device and method of forming are provided. In an illustrative embodiment, a gate all around (GAA) stacked nanosheet field effect transistor (FET) includes a plurality of stacked semiconductor channel nanosheet layers and a dummy nanosheet layer formed above a top one of the stacked semiconductor channel nanosheet layers, the dummy nanosheet formed from a dielectric material. The GAA stacked nanosheet FET also includes a high dielectric constant (high-k) material formed around each of the plurality of stacked semiconductor channel nanosheet layers and around the dummy nanosheet layer and a first work function (WF) metal formed around the plurality of stacked semiconductor channel nanosheet layers and the dummy nanosheet layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Alexander Reznicek
  • Patent number: 10748994
    Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 10748819
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by forming a gradient threshold voltage adjusting gate dielectric structure between the bottom drain region of the FET and the top source region of the FET. The gradient threshold voltage adjusting gate dielectric structure includes a doped interface high-k gate dielectric material that is located in proximity to the bottom drain region and a non-doped high-k dielectric material that is located in proximity to the top source region. The non-doped high-k dielectric material has a higher threshold voltage than the doped interface high-k gate dielectric.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, SangHoon Shin, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10748990
    Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek
  • Publication number: 20200258941
    Abstract: A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 13, 2020
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang, Pouya Hashemi
  • Publication number: 20200258786
    Abstract: A method is presented for attaining different gate dielectric thicknesses across a plurality of field effect transistor (FET) devices. The method includes forming interfacial and high-k dielectric layers around alternate semiconductor layers of the plurality of FET devices, pinching off gaps between the alternate semiconductor layers by depositing a high work function capping layer over the plurality of FET devices, selectively removing the high work function capping layer from a first set of the plurality of FET devices, depositing a sacrificial capping layer, with the sacrificial capping layer leaving gaps between the alternate semiconductor layers of the first set of the plurality of FET devices, depositing an oxygen blocking layer, and annealing the plurality of FET devices to create different gate dielectric thicknesses for each of the plurality of FET devices.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 13, 2020
    Inventors: Takashi Ando, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee, Pouya Hashemi