Abstract: A multilayered bottom electrode for a magnetic tunnel junction (MTJ) containing device is provided that includes, from bottom to top, a base segment having a first diameter and composed of a remaining portion of a first bottom electrode metal-containing layer, a middle segment having a second diameter and composed of a remaining portion of a second bottom electrode metal-containing layer, and an upper segment having a third diameter and composed of a remaining portion of a third bottom electrode metal-containing layer, wherein the first diameter is greater than the second diameter, and the third diameter is equal to, or less than, the second diameter. The wider base segment of each multilayered bottom electrode prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate. The plurality of fins each include a first portion having a first width, and a second portion having a second width greater than the first width. The method also includes forming a sacrificial layer on the substrate in a space between a first fin and a second fin of the plurality of fins, wherein the first fin and the second fin correspond to a vertical transistor. In the method, lower portions of the first and second fins are removed, and an epitaxial region is formed under remaining portions of the first and second fins. The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region.

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

Abstract: A first fin field effect transistor (FinFET) has an internal source/drain (S/D) with a facetted face that is connected to a dielectric side of a first RRAM. A second FinFET and RRAM structure are also disclosed. In some embodiments, an electrode contact side of each RRAM is connected in common to form a 2T2R device. The locations of one or more electrode points on the diamond-shaped, facetted surface of the bottom electrode accurately position electric fields through the dielectric to accurately and repeatably locate where the filaments/current paths are formed (or reset) through the RRAM dielectric. Material selection and accurate thickness of the RRAM dielectric determine the voltage at which the filaments/current paths are formed (or reset).

Abstract: A resistive random access memory (RRAM) structure includes top and bottom electrodes electrically coupled with first and second metal connection lines, respectively, the first and second metal connection lines providing electrical connection to the RRAM structure. A layer of resistive switching material is disposed between the top and bottom electrodes of the RRAM structure. The resistive switching material exhibits a measurable change in resistance under influence of at least an electric field and/or heat. Dielectric spacers are formed on sidewalls of at least the bottom electrode of the RRAM structure. The RRAM structure further includes a passivation layer formed on an upper surface of the dielectric spacers and covering at least a portion of sidewalls of the top electrode. The passivation layer is self-aligned with the first metal connection line.

Abstract: A replacement bottom electrode structure process is provided in which a patterned stack containing a MTJ pillar and a top electrode structure is fabricated and passivated on a sacrificial dielectric material plug that is embedded in a dielectric capping layer. The sacrificial dielectric material plug is then removed and replaced with a bottom electrode structure. The replacement bottom electrode structure process of the present application allows the MTJ patterning to be misalignment tolerate and fully eliminates the potential yield loss from the bottom electrode structure.

Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of first and second silicon germanium layers, and a plurality of silicon layers in a stacked configuration. The stacked configuration includes a repeating arrangement of a silicon layer stacked on an arrangement of at least one of the first and at least two of the second silicon germanium layers. The first and second silicon germanium layers are etched from exposed lateral sides, and plurality of first inner spacers are formed adjacent remaining portions of the first and second silicon germanium layers. Parts of the remaining portions of the second germanium layers are positioned between the first inner spacers and the silicon layers. The method also includes forming a plurality of second inner spacers, and removing the remaining portions of the first and second silicon germanium layers, leaving spaces between the first inner spacers and the silicon layers.

Abstract: A strained relaxed silicon germanium alloy buffer layer is employed in the present application to induce a tensile stain on each suspended semiconductor channel material nanosheet within a nanosheet material stack that is present in a long channel device region of a semiconductor substrate. The induced tensile strain keeps the suspended semiconductor channel material nanosheets that are present in long channel device region essentially straight in a lateral direction. Hence, reducing and even eliminating the sagging effect that can be caused by surface tension.

Abstract: A dielectric material structure is formed laterally adjacent to a bottom portion of a bottom electrode metal-containing portion that extends upward from an electrically conductive structure that is embedded in an interconnect dielectric material layer. The physically exposed top portion of the bottom electrode metal-containing portion is then trimmed to provide a bottom electrode of unitary construction (i.e., a single piece) that has a lower portion having a first diameter and an upper portion that has a second diameter that is greater than the first diameter. The presence of the dielectric material structure prevents tilting and/or bowing of the resultant bottom electrode. Thus, a stable bottom electrode is provided.

Abstract: An embodiment of the invention may include a method for of forming a semiconductor device and the resulting device. The method may include forming a gate dielectric on a gate region of a substrate. The method may include forming an inner dummy gate on a first portion of the gate dielectric. The method may include forming an outer dummy gate adjacent to the inner dummy gate on a second portion of the gate dielectric. The method may include forming spacers adjacent to the outer dummy gate. The method may include removing the outer dummy gate and depositing a first work function metal. The method may include removing the inner dummy gate and depositing a second work function metal.

Abstract: A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming an MTJ stack including a reference layer, a tunnel barrier layer formed on the reference layer, a free layer formed on the barrier layer, and a cap layer formed on the free layer. The method also includes performing ion beam etching (IBE) through each layer of the MTJ stack to form at least one MTJ pillar. The method also includes forming an isolation layer on sidewalls of at least the tunnel barrier layer, the isolation layer comprising a same material as that of the tunnel barrier layer. A combined width of the isolation layer and the tunnel barrier layer is equal to or greater than a width of at least one of the reference layer and the free layer.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, and forming a second magnetic tunnel junction stack on the spin conducting layer. The second magnetic tunnel junction stack has a width that is greater than a width of the first magnetic tunnel junction stack.

Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a conformal dielectric encapsulation liner is located on a sidewall of each of a MTJ pillar and an overlying top electrode, and a non-conformal dielectric encapsulation liner is located on the conformal dielectric encapsulation liner. This dual encapsulation liner structure prevents the bottom electrode of the MTJ containing device from being physically exposed thus eliminating the possibility that the bottom electrode can be a source of resputtered conductive metal particles that can deposit on a sidewall of the MTJ pillar. As such, electrical shorting is reduced in the MTJ containing device of the present application. Also, the dual encapsulation liner structure can mitigate chemical diffusion into the tunnel barrier material of the MTJ pillar.

Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.

Abstract: A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.

Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

Abstract: Semiconductor devices and methods of forming the same include forming first recesses in a first stack of alternating sacrificial layers and channel layers. A first inner spacer sub-layer is formed in the first recesses from a first dielectric material. A second inner spacer sub-layer is formed in the first recesses from a second dielectric material, different from the first dielectric material. The sacrificial layers and the first inner spacer sub-layer are replaced with a gate stack in contact with the second inner spacer sub-layer.

Abstract: A semiconductor structure including a nanosheet stack on a silicon germanium on insulator substrate, the nanosheet stack including alternating layers of a sacrificial semiconductor material and a semiconductor channel material vertically aligned and stacked one on top of another, a gate conductor orthogonal to the nanosheet stack and wrapping around the semiconductor channel material layers of the nanosheet stack, and a gate contact on the gate conductor layer adjacent to the nanosheet stack.

Abstract: A semiconductor device including at least one nanosheet and epitaxial source and drain regions are present on opposing ends of the at least one nanosheet. A gate structure is present on a channel of the at least one nanosheet. The gate structure includes a first work function metal gate portion present at a junction portion of the source and drain regions that interfaces with the channel portion of the at least one nanosheet, and a second work function metal gate portion present on a central portion of the channel of the at least one nanosheet. The amount of metal containing nitride in the second work function metal gate portion is greater than an amount of metal containing nitride in the first work function metal gate portion. The device further includes a rotated T-shaped dielectric spacer present between the gate structure and the epitaxial source and drain regions.