Abstract: Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.

Abstract: Semiconductor devices and method of forming the same include recessing sacrificial layers relative to the channel layers, in a stack of vertically aligned, alternating sacrificial layers and channel layers, to form first recesses. A dual-layer dielectric is deposited that includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the first recesses. The first dielectric material is recessed relative to the second dielectric material to form second recesses. Additional second dielectric material is deposited to fill the second recesses. The second dielectric material and the additional second dielectric material is etched away to create air gaps.

Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A method of forming a nanosheet field effect transistor device is provided. The method includes forming a stack of alternating sacrificial layer segments and nanosheet layer segments on a substrate. The method further includes removing the sacrificial layer segments to form channels on opposite sides of the nanosheet layer segments. The method further includes depositing a gate dielectric layer around each of the nanosheet layer segments, and forming a work function material block on the gate dielectric layer to form a gate-all-around structure on the nanosheet layer segments. The method further includes forming a capping layer on the work function material block.

Abstract: A bottom electrode structure for a magnetic tunnel junction (MTJ) containing device is provided. The bottom electrode structure includes a mesa portion that is laterally surrounded by a recessed region. The recessed region of the bottom electrode structure is laterally adjacent to a dielectric material, and a MTJ pillar is located on the mesa portion of the bottom electrode structure. Such a configuration shields the recessed region from impinging ions thus preventing deposition of resputtered conductive metal particles from the bottom electrode onto the MTJ pillar.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a second magnetic tunnel junction stack on the spin conducting layer, and forming a dielectric spacer layer on surfaces of the spin conducting layer and the second magnetic tunnel junction stack. The second magnetic tunnel junction stack has a width that is less than a width of the first magnetic tunnel junction stack. Also, a width of the spin conducting layer increases in a thickness direction from a first side of the spin conducting layer adjacent to the second magnetic tunnel junction stack to a second side of the spin conducting layer adjacent to the first magnetic tunnel junction stack.

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

Abstract: A cross-bar ReRAM comprising a substrate, a plurality of first columns extending parallel to each other on the top surface of the substrate, wherein each of the plurality of the first columns includes a resistive random-access memory (ReRAM) stack comprised of a plurality of layers. A plurality of second columns extending parallel to each other and the plurality of second columns extending perpendicular to the plurality of first columns, wherein the plurality of second columns is located on top of the plurality of first columns, such that the plurality of second columns crosses over the plurality of first columns. A dielectric layer filling in the space between the plurality of first columns and the plurality of second columns, wherein the dielectric layer is in direct contact with a sidewall of each of the plurality layers of the ReRAM stack.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, and forming a second magnetic tunnel junction stack on the spin conducting layer. The second magnetic tunnel junction stack has a width that is greater than a width of the first magnetic tunnel junction stack.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: An embodiment of the invention may include a method for of forming a semiconductor device and the resulting device. The method may include forming a gate dielectric on a gate region of a substrate. The method may include forming an inner dummy gate on a first portion of the gate dielectric. The method may include forming an outer dummy gate adjacent to the inner dummy gate on a second portion of the gate dielectric. The method may include forming spacers adjacent to the outer dummy gate. The method may include removing the outer dummy gate and depositing a first work function metal. The method may include removing the inner dummy gate and depositing a second work function metal.

Abstract: A magnetic tunnel junction (MTJ) device includes a cylindrically-shaped pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a magnetization that is fixed. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.

Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

Abstract: A sub-micrometer pressure sensor is provided that includes a multilayered magnetic tunnel junction (MTJ) pillar that contains a non-magnetic metallic spacer separating a first magnetic free layer from a second magnetic free layer. The presence of the non-magnetic metallic spacer in the multilayered MTJ pillar improves the sensitivity without compromising area, and makes the pressure sensor binary (either “on” or “off”) with little or no drift, and sensitivity change over time. Moreover, the resistivity switch in such a pressure sensor is instantly and a low error rate is observed.

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of first and second silicon germanium layers, and a plurality of silicon layers in a stacked configuration. The stacked configuration includes a repeating arrangement of a silicon layer stacked on an arrangement of at least one of the first and at least two of the second silicon germanium layers. The first and second silicon germanium layers are etched from exposed lateral sides, and plurality of first inner spacers are formed adjacent remaining portions of the first and second silicon germanium layers. Parts of the remaining portions of the second germanium layers are positioned between the first inner spacers and the silicon layers. The method also includes forming a plurality of second inner spacers, and removing the remaining portions of the first and second silicon germanium layers, leaving spaces between the first inner spacers and the silicon layers.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate. The plurality of fins each include a first portion having a first width, and a second portion having a second width greater than the first width. The method also includes forming a sacrificial layer on the substrate in a space between a first fin and a second fin of the plurality of fins, wherein the first fin and the second fin correspond to a vertical transistor. In the method, lower portions of the first and second fins are removed, and an epitaxial region is formed under remaining portions of the first and second fins. The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region.