Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction
    Patent number: 10396152
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Very narrow aspect ratio trapping trench structure with smooth trench sidewalls
    Patent number: 10396075
    Abstract: After forming a plurality of semiconductor fins that are separated from one another by trenches on a substrate, the semiconductor fins are fully or partially oxidized to provide semiconductor oxide portions. The volume expansion caused by the oxidation of the semiconductor fins reduces widths of the trenches, thereby providing narrowed trenches for formation of epitaxial semiconductor fins using aspect ratio trapping techniques.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
    Patent number: 10396214
    Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Method for forming a semiconductor structure containing high mobility semiconductor channel materials
    Patent number: 10395996
    Abstract: A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Vertical transistor pass gate device
    Patent number: 10396198
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Lateral bipolar junction transistor with abrupt junction and compound buried oxide
    Patent number: 10396154
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20190259750
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Vertical field effect transistor (VFET) programmable complementary metal oxide semiconductor inverter
    Patent number: 10388648
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation
    Patent number: 10388727
    Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek
  • Vertically stacked NFETS and PFETS with gate-all-around structure
    Patent number: 10381438
    Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek
  • Enhanced field bipolar resistive RAM integrated with FDSOI technology
    Patent number: 10374039
    Abstract: A resistive random access memory stack is formed on a surface of a faceted drain-side structure that is present on one side of a functional gate structure. The functional gate structure and the faceted drain-side structure are located on a topmost surface of a fully depleted semiconductor channel material layer. In some embodiments, the resistive random access memory stack includes a bottom electrode, a resistive switching layer and a top electrode. In other embodiments, the resistive random access memory stack includes a resistive switching layer and a top electrode. In such an embodiment, a drain-side metal semiconductor alloy of the faceted drain-side structure is used as the bottom electrode of the resistive random access memory device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • Diode connected vertical transistor
    Patent number: 10366984
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • STRAINED SILICON GERMANIUM FIN WITH BLOCK SOURCE/DRAIN EPITAXY AND IMPROVED OVERLAY CAPACITANCE
    Publication number: 20190229195
    Abstract: A semiconductor structure is provided including a strained silicon germanium alloy fin that can be employed as a channel material for a FinFET device and having a gate spacer including a lower portion that fills in a undercut region that lies adjacent to the strained silicon germanium alloy fin and beneath raised source/drain (S/D) structures and silicon pedestal structures that can provide improved overlay capacitance.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • STACKED FIELD-EFFECT TRANSISTORS (FETS) WITH SHARED AND NON-SHARED GATES
    Publication number: 20190229021
    Abstract: A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
    Type: Application
    Filed: April 3, 2019
    Publication date: July 25, 2019
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Vertical transistor transmission gate with adjacent NFET and PFET
    Patent number: 10361199
    Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Stacked field-effect transistors (FETs) with shared and non-shared gates
    Patent number: 10361131
    Abstract: A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Fabrication of vertical fin transistor with multiple threshold voltages
    Patent number: 10361301
    Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • STACKED FINFET EEPROM
    Publication number: 20190214398
    Abstract: A method for integrating a stack of fins to form an electrically erasable programmable read-only memory (EEPROM) device is presented. The method includes forming a stack of at least a first fin structure and a second fin structure over a semiconductor substrate, forming a sacrificial gate straddling the stack of at least the first fin structure and the second fin structure, forming a first conductivity type source/drain region to the first fin structure, and forming a second conductivity type source/drain to the second fin structure. The method further includes removing the sacrificial gate to form a gate opening, and forming a single floating gate in communication with a channel for each of the first and second fin structures.
    Type: Application
    Filed: March 13, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • DIODE CONNECTED VERTICAL TRANSISTOR
    Publication number: 20190214384
    Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek
  • Germanium dual-fin field effect transistor
    Patent number: 10347539
    Abstract: In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek