Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical FET with differential top spacer
    Patent number: 10559676
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • Formation of self-limited inner spacer for gate-all-around nanosheet FET
    Patent number: 10553679
    Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek, Pouya Hashemi
  • Full air-gap spacers for gate-all-around nanosheet field effect transistors
    Patent number: 10553696
    Abstract: Semiconductor devices and method of forming the same include forming a stack of vertically aligned, alternating layers including sacrificial layers and channel layers. The sacrificial layers are recessed relative to the channel layers to form recesses. A dual-layer dielectric is deposited. The dual-layer dielectric includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the recesses. The first dielectric material is recessed relative to the second dielectric material. The second dielectric material is etched away to create air gaps. Outer spacers are formed using a third dielectric material that pinches off, preventing the third dielectric material from filling the air gaps.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Vertically stacked dual channel nanosheet devices
    Patent number: 10553678
    Abstract: A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • LONG CHANNEL OPTIMIZATION FOR GATE-ALL-AROUND TRANSISTORS
    Publication number: 20200035820
    Abstract: A strained relaxed silicon germanium alloy buffer layer is employed in the present application to induce a tensile stain on each suspended semiconductor channel material nanosheet within a nanosheet material stack that is present in a long channel device region of a semiconductor substrate. The induced tensile strain keeps the suspended semiconductor channel material nanosheets that are present in long channel device region essentially straight in a lateral direction. Hence, reducing and even eliminating the sagging effect that can be caused by surface tension.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 30, 2020
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek
  • TIGHTLY INTEGRATED 1T1R ReRAM FOR PLANAR TECHNOLOGY
    Publication number: 20200035915
    Abstract: A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Inventors: Alexander Reznicek, Takashi Ando, Pouya Hashemi
  • Vertically stacked nFET and pFET with dual work function
    Patent number: 10546925
    Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques
    Patent number: 10546928
    Abstract: A semiconductor structure that includes: a substrate, a twin vertical punch-through stopper layer structure connected to the substrate, and a plurality of nanosheets connected to and supported by the twin vertical punch-through stopper structure and isolated from the substrate by an insulating dielectric.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Karthik Balakrishnan, Alexander Reznicek, Mahmoud Khojasteh
  • Vertical transistor transmission gate with adjacent NFET and PFET
    Patent number: 10546857
    Abstract: A complementary metal oxide semiconductor (CMOS) vertical transistor structure with closely spaced p-type and n-type vertical field effect transistors (FETs) is provided. After forming a dielectric material portion contacting a proximal sidewall of a first semiconductor fin for formation of a p-type vertical FET and a proximal sidewall of a second semiconductor fin for formation of an n-type vertical FET, a first gate structure is formed contacting a distal sidewall of the first semiconductor fin, and a second gate structure is formed contacting a distal sidewall of the second semiconductor fin. Because no gate structures are formed between the first and second semiconductor fins, the p-type vertical FET is spaced from the n-type FET only by the dielectric material portion.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Nickel-silicon fuse for FinFET structures
    Patent number: 10541203
    Abstract: Semiconductor fuses include a semiconductor fin having a metallized region between two non-metallized regions. Conductive layers are formed on the semiconductor fin above the two non-metallized regions. A dielectric layer is formed over the metallized region, between the conductive layers.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, Alexander Reznicek
  • CO-INTEGRATED CHANNEL AND GATE FORMATION SCHEME FOR NANOSHEET TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES
    Publication number: 20200020690
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventors: Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi, Alexander Reznicek
  • VERTICALLY STACKED DUAL CHANNEL NANOSHEET DEVICES
    Publication number: 20200020768
    Abstract: A semiconductor structure having electrostatic control and a low threshold voltage is provided. The structure includes an nFET containing vertically stacked and suspended Si channel material nanosheets stacked vertically above a pFET containing vertically stacked and suspended SiGe channel material nanosheets. The vertically stacked nFET and pFET include a single work function metal.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando, Alexander Reznicek
  • FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE
    Publication number: 20200020539
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Cointegration of III-V channels and germanium channels for vertical field effect transistors
    Patent number: 10535570
    Abstract: Methods for forming cointegrated III-V and Ge channels for vertical field effect transistors are described. Aspects of the invention include forming a first fin and a second fin on a substrate, wherein the first fin includes a first material including a first semiconductor material at a first concentration level, and wherein the second fin includes a second material including a second semiconductor material at a second concentration. A condensation oxidation is performed to increase the first concentration level to a targeted first final concentration level and increase the second concentration level to a targeted second final concentration level. The second fin is replaced with a third fin including a third material including a combination of a group III element with a group V element.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • FORMATION OF WRAP-AROUND-CONTACT TO REDUCE CONTACT RESISTIVITY
    Publication number: 20200013900
    Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 9, 2020
    Inventors: Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando, Pouya Hashemi
  • Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
    Patent number: 10529573
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan
  • Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy
    Patent number: 10529716
    Abstract: A method is presented for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET). The method includes constructing a first set fins from a first material, constructing a second set of fins from a second material, forming a source region between the first set of fins, and forming a drain region between the second set of fins, the source region composed of a different material than the drain region. The method further includes depositing a first high-k metal gate over the first set of fins and depositing a second high-k metal gate over the second set of fins, the second high-k metal gate being different than the first high-k metal gate such that the asymmetric threshold voltage is present along the channel of the VTFET in a region defined at the bottom of the first and second set of fins.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Jingyun Zhang, Takashi Ando, Alexander Reznicek, Pouya Hashemi
  • Multiple work function device using GeOx/TiN cap on work function setting metal
    Patent number: 10529798
    Abstract: A method is presented for tuning work functions of transistors. The method includes forming a work function stack over a semiconductor substrate, depositing a germanium oxide layer and a barrier layer over the work function stack, and annealing the germanium oxide layer to desorb oxygen therefrom to trigger oxidation of at least one conducting layer of the work function stack. The work function stack includes three layers, that is, a first layer being a TiN layer, a second layer being a titanium aluminum carbon (TiAlC) layer, and a third layer being a second TiN layer.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • CO-INTEGRATION OF HIGH CARRIER MOBILILTY PFET AND NFET DEVICES ON THE SAME SUBSTRATE USING LOW TEMPERATURE CONDENSATION
    Publication number: 20200006146
    Abstract: Embodiments of the invention are directed to a method of fabricating semiconductor devices. A non-limiting example of the method includes forming a first fin in a p-type field effect transistor (PFET) region of a substrate, wherein the first fin includes a first material that includes a first type of semiconductor material at a first concentration level. A second fin is formed in an n-type FET (NFET) region of the substrate, wherein the second fin includes a second semiconductor material that includes a III-V compound. Condensation operations are performed, wherein the condensation operations are configured to increase the first concentration level in at least a portion of the first fin to a targeted final concentration level.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee
  • CO-INTEGRATION OF HIGH CARRIER MOBILILTY PFET AND NFET DEVICES ON THE SAME SUBSTRATE USING LOW TEMPERATURE CONDENSATION
    Publication number: 20200006147
    Abstract: Embodiments of the invention are directed to fin-based field effect transistor (FET) devices formed on a substrate. In a non-limiting example, the devices a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin includes a top region, a central region, and a bottom region. The central region of the first fin includes an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level. The top region of the first fin includes the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level, along with an anneal-induced second concentration level of the first type of semiconductor material. A final concentration level of the first type of semiconductor material in the top region includes the first concentration level and the second concentration level.
    Type: Application
    Filed: September 9, 2019
    Publication date: January 2, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee