Patents by Inventor Pouya Hashemi

Pouya Hashemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FORMATION OF WRAP-AROUND-CONTACT FOR GATE-ALL-AROUND NANOSHEET FET
    Publication number: 20190326395
    Abstract: A semiconductor device includes a substrate material with a semiconductor material with a predetermined crystal orientation, a gate stack having a plurality of nanosheet channel layers, each nanosheet channel layer being controlled by metal gate layers located above and below the nanosheet channel layer, each nanosheet channel layer having the same semiconductor material and crystal orientation as that of the substrate, and a source/drain region on opposite sides of the gate stack. Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • FABRICATION OF PERFECTLY SYMMETRIC GATE-ALL-AROUND FET ON SUSPENDED NANOWIRE USING INTERFACE INTERACTION
    Publication number: 20190326396
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Vertical FET with Differential Top Spacer
    Publication number: 20190326410
    Abstract: VTFET devices having a differential top spacer are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer including NFET and PFET fins; forming bottom source and drains at a base of the NFET/PFET fins; forming bottom spacers on the bottom source and drains; forming gate stacks alongside the NFET/PFET fins that include a same workfunction metal on top of a gate dielectric; annealing the gate stacks which generates oxygen vacancies in the gate dielectric; forming top spacers that include an oxide spacer layer in contact with only the gate stacks alongside the PFET fins, wherein the oxide spacer layer supplies oxygen filling the oxygen vacancies in the gate dielectric only in the gate stacks alongside the PFET fins; and forming top source and drains above the gate stacks at the tops of the NFET/PFET fins. A VTFET device is also provided.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Takashi Ando, Choonghyun Lee, Jingyun Zhang, Pouya Hashemi
  • LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
    Publication number: 20190326397
    Abstract: A lateral bipolar junction transistor (LBJT) device that may include a dielectric stack including a pedestal of a base region passivating dielectric and a nucleation dielectric layer; and a base region composed of a germanium containing material or a type III-V semiconductor material in contact with the pedestal of the base region passivating dielectric. An emitter region and collector region may be present on opposing sides of the base region contacting a sidewall of the pedestal of the base region passivating dielectric and an upper surface of the nucleation dielectric layer.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Kevin K. Chan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Fin replacement in a field-effect transistor
    Patent number: 10453959
    Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • High density antifuse co-integrated with vertical FET
    Patent number: 10453792
    Abstract: A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Pouya Hashemi, Miaomiao Wang, Takashi Ando
  • VERTICALLY STACKED NFETS AND PFETS WITH GATE-ALL-AROUND STRUCTURE
    Publication number: 20190319095
    Abstract: A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 17, 2019
    Inventors: Jingyun Zhang, Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek
  • HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS
    Publication number: 20190312044
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS HAVING GERMANIUM CHANNEL SURFACES
    Publication number: 20190311958
    Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Choonghyun Lee, Pouya Hashemi, Takashi Ando
  • VERTICAL TRANSISTOR PASS GATE DEVICE
    Publication number: 20190312141
    Abstract: A semiconductor device including a fin structure present on a supporting substrate to provide a vertically orientated channel region. A first source/drain region having a first epitaxial material with a diamond shaped geometry is present at first end of the fin structure that is present on the supporting substrate. A second source/drain region having a second epitaxial material with said diamond shaped geometry that is present at the second end of the fin structure. A same geometry for the first and second epitaxial material of the first and second source/drain regions provides a symmetrical device.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • High density programmable e-fuse co-integrated with vertical FETs
    Patent number: 10438956
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • VERTICAL FIELD EFFECT TRANSISTOR (VFET) PROGRAMMABLE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INVERTER
    Publication number: 20190304968
    Abstract: A method of forming a semiconductor inverter that includes forming a first conductivity type vertically orientated semiconductor device in a first region of a substrate, and a second conductivity type vertically orientated semiconductor device in a second region of the substrate. A common contact is formed electrically connecting an upper source and drain region for the first conductivity type vertically orientated semiconductor device to an upper source and drain region of the second conductivity type vertically orientated semiconductor device. The common electrical contact providing an output for the inverter. The method may further include forming a first electrical contact to a first gate structure to a first of the first and second conductivity type vertically orientated semiconductor device to provide an input for the inverter.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • HIGH DENSITY ANTIFUSE CO-INTEGRATED WITH VERTICAL FET
    Publication number: 20190295949
    Abstract: A semiconductor device including an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and including an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Inventors: Alexander REZNICEK, Pouya HASHEMI, Miaomiao WANG, Takashi ANDO
  • STACKED INDIUM GALLIUM ARSENIDE NANOSHEETS ON SILICON WITH BOTTOM TRAPEZOID ISOLATION
    Publication number: 20190296106
    Abstract: A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Takashi Ando, Pouya Hashemi, Mahmoud Khojasteh, Alexander Reznicek
  • HIGH DENSITY ANTIFUSE CO-INTEGRATED WITH VERTICAL FET
    Publication number: 20190295950
    Abstract: A semiconductor device comprising an anti-fuse is disclosed. The semiconductor anti-fuse includes a highly doped source of a first conductivity type overlying a substrate. The semiconductor anti-fuse further includes a counter-doped layer of a second conductivity type arranged between the highly doped source and the substrate. The semiconductor anti-fuse further includes a highly doped fuse region extending over the highly doped source and comprising an epitaxial growth, the highly doped fuse region implanted with ions.
    Type: Application
    Filed: May 14, 2019
    Publication date: September 26, 2019
    Inventors: Alexander REZNICEK, Pouya HASHEMI, Miaomiao WANG, Takashi ANDO
  • Decoupling capacitor on strain relaxation buffer layer
    Patent number: 10424585
    Abstract: An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Single column compound semiconductor bipolar junction transistor fabricated on III-V compound semiconductor surface
    Patent number: 10424650
    Abstract: A vertical, single column compound semiconductor bipolar junction transistor device includes an all-around extrinsic base. Homojunction and heterojunction devices are formed using III-V compound semiconductor materials with appropriate bandgaps. Fabrication of the transistor device includes epitaxially growing a III-V compound semiconductor base region on a heavily doped III-V compound semiconductor bottom layer. A polycrystalline emitter/collector layer and the all-around extrinsic base are grown on the base region.
    Type: Grant
    Filed: June 16, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • MULTIPLE WORK FUNCTION NANOSHEET FIELD EFFECT TRANSISTOR USING SACRIFICIAL SILICON GERMANIUM GROWTH
    Publication number: 20190280107
    Abstract: A method of forming a semiconductor device that includes forming a stack of nanosheets composed of a semiconductor material; and forming a sacrificial layer of a work function adjusting material on the semiconductor material of the stack of nanosheets. In a following step, the work function adjusting material is mixed into the semiconductor material on at least a channel surface of nanosheets. The sacrificial layer is removed. An interfacial oxide layer is formed including elements from the semiconductor material and the work function adjusting layer on said at least the channel surface of the stack of nanosheets. A gate structure including a gate dielectric is formed on the interfacial oxide that is present on the channel surface of the nanosheets.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Takashi Ando, Choonghyun Lee, Pouya Hashemi
  • Fabricating contacts of a CMOS structure
    Patent number: 10410926
    Abstract: The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi
  • Method and structure for incorporating strain in nanosheet devices
    Patent number: 10396202
    Abstract: A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek