Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

Abstract: The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.

Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.

Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.

Abstract: A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.

Abstract: A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs.

Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.