Abstract: A ramp generator circuit for generating sawtooth waveforms based on a clock signal may include an operational amplifier, a first switched capacitor device within a first feedback path of the operational amplifier, and a first plurality of switch devices within the first feedback path, whereby upon actuation of the first plurality of switches, the first switched capacitor generates first ramp waveforms during first alternate clock periods of the clock signal. The circuit may also include a second switched capacitor device within a second feedback path of the operational amplifier, and a second plurality of switch devices within the second feedback path, whereby upon actuation of the second plurality of switches, the second switched capacitor generates second ramp waveforms during second alternate clock periods of the clock signal. The first alternate clock periods of the clock are followed by an adjacent one of the second alternate clock periods of the clock.

Abstract: A system and method of allocating a job submission for a computational task to a set of distributed server farms each having at least one processing entity comprising; receiving a workload request from at least one processing entity for submission to at least one of the set of distributed server farms; using at least one or more conditions associated with the computational task for accepting or rejecting at least one of the server farms to which the job submission is to be allocated; determining a server farm that can optimize the one or more conditions; and dispatching the job submission to the server farm which optimizes the at least one of the one or more conditions associated with the computational task and used for selecting the at least one of the server farms.

Abstract: An improved programmable duty cycle generator and method of operation. In one aspect, the generated output signal duty cycle is not measured, but rather is generated based on a predetermined value. Saw tooth generator/Integrator schemes are used to create the saw type waveforms of the incoming frequency which in conjunction with DAC is used to create the desired duty cycle. The improved programmable duty cycle signal generator for placement in key pinch points of a critical path where precise duty cycle definition is needed.

Abstract: An improved programmable duty cycle generator and method of operation. In one aspect, the generated output signal duty cycle is not measured, but rather is generated based on a predetermined value. Saw tooth generator/Integrator schemes are used to create the saw type waveforms of the incoming frequency which in conjunction with DAC is used to create the desired duty cycle. The improved programmable duty cycle signal generator for placement in key pinch points of a critical path where precise duty cycle definition is needed.

Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.

Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Abstract: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.

Abstract: Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Abstract: A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.

Abstract: A slew rate control circuit generates a slew-rate controlled clock signal from an input clock signal based on a feedback control mechanism. The feedback control mechanism uses the input clock signal duty cycle characteristics as a reference for controlling and maintaining an optimum slew rate for the slew-rate controlled clock signal. By using the input clock signal as a reference, the slew-rate controlled clock signal is dynamically measured and periodically adjusted over each cycle of the input clock signal.

Abstract: A delay line with cell by cell power down capability and methods of use are provided. The delay cell includes a first gate transistor coupled to a voltage supply, a second gate transistor coupled to ground, and a reset signal provided to at least one of the first gate transistor and the second gate transistor. The reset signal turns the delay cell on and off.

Abstract: Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: Leakage tolerant delay locked loop (DLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant DLL circuit device are provided. Embodiments include a DLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, and a voltage controlled buffer (VCB). The secondary correction circuit is configured to generate and provide secondary error-delay signals to the error controller. The secondary correction circuit includes multiple error generators. Each error generator is configured to generate a secondary error-delay signal in response to detecting a particular edge of an output phase signal from the VCB. The primary loop is configured to control a phase adjustment based on at least one of a first error-delay-increase signal, a first error-delay-decrease signal, and the secondary error-delay signals.

Abstract: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.

Abstract: Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.

Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.

Abstract: A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.

Abstract: A differential system producing differential signals with offset cancellation utilizing a double differential input pair system is disclosed. It uses two parallel differential transistor pairs which are intentionally skewed. Nominally, the differential pairs are skewed in opposite direction from each, but with equal magnitude, so that the combination of the two differential pairs is nominally balanced. The current through each differential pair is then increased or decreased until any offset is sufficiently cancelled, using a selection means for providing an equi-potential value to first and second differential inputs in a calibration mode of the system and a comparison means for comparing first and second differential outputs in a calibration mode to determine the offset of the system.

Abstract: Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.