Patents by Inventor Pradeep Thiagarajan
Pradeep Thiagarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080186054Abstract: A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, a design structure for a exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.Type: ApplicationFiled: August 31, 2007Publication date: August 7, 2008Inventors: Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
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Patent number: 7403039Abstract: A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.Type: GrantFiled: February 2, 2007Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
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Publication number: 20080143416Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Serafino Bueti, Hayden C. Cranford, Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
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Publication number: 20080148204Abstract: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Serafino Bueti, Hayden C. Cranford, Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
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Patent number: 7378890Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.Type: GrantFiled: September 19, 2007Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: John S. Austin, Ram Kelkar, Pradeep Thiagarajan
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Patent number: 7362138Abstract: A multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to full-swing converter mode. The operating modes of the multimode circuit may be dynamically selectable. One or more multimode circuits may be part of a configurable distribution path for controlling the performance of a signal distribution path or tree of an integrated circuit.Type: GrantFiled: December 20, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Igor Arsovski, Anthony R. Bonaccio, Hayden C. Cranford, Jr., Joseph A. Iadanza, Pradeep Thiagarajan, Sebastian T. Ventrone
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Patent number: 7342429Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.Type: GrantFiled: January 5, 2006Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: John S. Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20080007310Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.Type: ApplicationFiled: September 19, 2007Publication date: January 10, 2008Inventors: John Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20070257723Abstract: A design structure comprising a voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.Type: ApplicationFiled: July 16, 2007Publication date: November 8, 2007Inventors: Ken Short, Pradeep Thiagarajan
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Patent number: 7288981Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.Type: GrantFiled: January 12, 2006Date of Patent: October 30, 2007Assignee: International Business Machines CorporationInventors: Kenneth Dean Short, Pradeep Thiagarajan
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Publication number: 20070159859Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.Type: ApplicationFiled: January 12, 2006Publication date: July 12, 2007Inventors: Kenneth Short, Pradeep Thiagarajan
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Patent number: 7180973Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: GrantFiled: March 14, 2006Date of Patent: February 20, 2007Assignee: International Business Machines CorporationInventors: John S. Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20060158237Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: ApplicationFiled: March 14, 2006Publication date: July 20, 2006Applicant: International Business Machines CorporationInventors: John Austin, Ram Kelkar, Pradeep Thiagarajan
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Patent number: 7075350Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: GrantFiled: March 2, 2005Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: John S. Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20060109947Abstract: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.Type: ApplicationFiled: January 5, 2006Publication date: May 25, 2006Applicant: International Business Machines CorporationInventors: John Austin, Ram Kelkar, Pradeep Thiagarajan
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Patent number: 7049864Abstract: A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.Type: GrantFiled: June 18, 2004Date of Patent: May 23, 2006Assignee: International Business Machines CorporationInventors: Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20050280449Abstract: A digital frequency divider apparatus includes a plurality of next-state generator elements receiving an input clock signal thereto, and configured to generate a next value for each of a corresponding plurality of internal state variables. A plurality of flip-flop elements is configured to store the generated next values for the plurality of internal state variables, the plurality of flip-flop elements further configured to provide a present value of the plurality of internal state variables to the next-state generator elements through a feedback path therebetween. The generated next values for the plurality of internal state variables are based upon the present values of the plurality of internal state variables and the input clock signal.Type: ApplicationFiled: June 18, 2004Publication date: December 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ram Kelkar, Pradeep Thiagarajan
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Patent number: 6917662Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: GrantFiled: September 11, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: John S. Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20050146362Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: ApplicationFiled: March 2, 2005Publication date: July 7, 2005Inventors: John Austin, Ram Kelkar, Pradeep Thiagarajan
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Publication number: 20050057285Abstract: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.Type: ApplicationFiled: September 11, 2003Publication date: March 17, 2005Applicant: International Business Machines CorporationInventors: John Austin, Ram Kelkar, Pradeep Thiagarajan