Abstract: In accordance with one embodiment, a fan controller operates in a standard mode when main power is provided to the power supply unit in which speed of the fan is controlled in response to a primary pulse width modulation (PWM) signal from a power controller. A loss of the main power to the power supply unit may be detected at a logic circuit, which provides a secondary PWM signal to the fan controller in response to the loss of the main power. In certain embodiments, the fan controller is operated in a power loss mode in response to the secondary PWM signal to direct the speed of the fan to a low-power consumption target speed.

Abstract: A fixed cutting structure-composite cone drill bit includes a drill bit body, a fixed cutting structure, and at least one cone. The cone and the fixed cutting structure are disposed on the drill bit body. The cone is rotatably connected to the drill bit body by means of a bearing structure. The distance from the outermost tooth or back cone of the at least one cone to the front side surface of the fixed cutting structure La??R/3, and the distance from the outermost tooth or back cone of the at least one cone to the rear side surface of the fixed cutting structure Lb??R/3. In the composite drill bit, the distance from the cone to the front/rear side surface of the fixed cutting structure is short, the gap between the cone and the fixed cutting structure is small, transition between cutting structure is smooth.

Abstract: The present disclosure belongs to the technical field of power generators, and in particular relates to a marine support column structure with power generation function. The support column structure solves technical problems that existing marine power generators can only generate power with single energy and have few functions and so on. The marine support column structure with power generation function includes a column body. The support column structure of the present disclosure is capable of generating power with sea wind and waves, and is further capable of serving as a guardrail.

Abstract: An image sensor includes one or more photodiodes disposed in a semiconductor material to receive image light and generate image charge, and a floating diffusion to receive the image charge from the one or more photodiodes. One or more transfer transistors is coupled to transfer image charge in the one or more photodiodes to the floating diffusion, and a source follower transistor is coupled to amplify the image charge in the floating diffusion. The source follower includes a gate electrode (coupled to the floating diffusion), source and drain electrodes, and an active region disposed in the semiconductor material between the source and drain electrodes. A dielectric material is disposed between the gate electrode and the active region and has a first thickness and a second thickness. The second thickness is greater than the first thickness, and the second thickness is disposed closer to the drain electrode than the first thickness.

Abstract: An inverting apparatus comprises: a DC port; an AC port; five switches; a first capacitor coupled between the first terminal of the second switch and the second terminal of the fourth switch; and a free-wheeling element coupled between the second terminal of the third switch and the second terminal of the fifth switch; wherein the five switches are controlled so that the device can switch among a plurality of operating modes and transmit active or reactive power to a power grid.

Abstract: Backside illuminated sensor pixel structure. In one embodiment, an image sensor includes a plurality of photodiodes arranged in rows and columns of a pixel array that are disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. The individual photodiodes have a diffusion region formed in an epitaxial region and a plurality of storage nodes (SGs) that are disposed on the front side of the semiconductor substrate and formed in the epitaxial region. An opaque isolation layer having a plurality of opaque isolation elements is disposed proximate to the front side of the semiconductor substrate and proximate to the diffusion region of the plurality of photodiodes. The opaque isolation elements are configured to block a path of incoming light from the backside of the semiconductor substrate toward the storage nodes.

Abstract: Backside illuminated sensor pixel structure. In one embodiment, an image sensor includes a plurality of photodiodes arranged in rows and columns of a pixel array that are disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. The individual photodiodes have a diffusion region formed in an epitaxial region and a plurality of storage nodes (SGs) that are disposed on the front side of the semiconductor substrate and formed in the epitaxial region. An opaque isolation layer having a plurality of opaque isolation elements is disposed proximate to the front side of the semiconductor substrate and proximate to the diffusion region of the plurality of photodiodes. The opaque isolation elements are configured to block a path of incoming light from the backside of the semiconductor substrate toward the storage nodes.

Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

Abstract: A pixel array includes a semiconductor substrate, a plurality of isolation layer segments, and a plurality of photodiodes. Each of the plurality of isolation layer segments extends through the semiconductor substrate in a first direction. Each of the plurality of isolation layer segments encloses a portion of the semiconductor substrate in a plane perpendicular to the first direction. The plurality of isolation layer segments form a grid that defines a plurality of isolated sections of the semiconductor substrate. The plurality of isolated sections of the semiconductor substrate include the portions of the semiconductor substrate. Each of the photodiodes is formed in a respective one of the plurality of isolated sections of the semiconductor substrate.

Abstract: An image sensor includes a substrate. An array of photodiodes is disposed in the substrate. A plurality of spacers is arranged in a spacer pattern. At least one spacer of the plurality of spacers has an aspect ratio of 18:1 or greater. A buffer layer is disposed between the substrate and the spacer pattern. An array of color filters is disposed in the spacer pattern.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.

Abstract: An information handling system includes a voltage regulator, a device, and a controller. The voltage regulator provides an output voltage to power on the device. The controller includes a voltage enable sense line. The controller provides a signal to enable the voltage regulator on the voltage enable sense line at a first voltage associated with a first state. The controller also monitors a voltage level on the voltage enable sense line, and determines whether the voltage level of the voltage enable sense line has changed to a second voltage level associated with a second state. In response to the voltage level on the voltage enable sense line changing to the second voltage level, the controller detects that the output voltage is fully turned on and provided to the device.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA and a card BMC. The FPGA is programmed with a plurality of accelerated function units (AFUs) to perform processing tasks for the processor. The card BMC receives a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU, halts the first processing task in response to the first indication, receives a second AFU from the system BMC, and reprograms the FPGA with the second AFU.

Abstract: The present disclosure provides a return gas prevention device for a drainage pipe, belonging to the technical field of drainage pipes. The device realizes two functions of water seal and a check valve simultaneously, as well as prevents gas channeling in a drainage process.

Abstract: Disclosed in the present invention is a tail gas treatment catalyst. The catalyst consists of a carrier, a first catalyst, and a second catalyst. The first catalyst and the second catalyst are provided on both ends of the carrier. The first catalyst can purify pollutants in tail gas. The second catalyst can purify a byproduct, ammonia, obtained by the purification by the first catalyst and pollutants that are not completely purified by the first catalyst. The second catalyst is of a double-layer structure; the lower layer consists of an oxygen storage material, aluminum oxide, and a second active component; the second active component is a composition of Pt and Pd, or a composition of Ce, Fe, Ni and Cu; the upper layer consists of a molecular sieve and a third active component; the third active component is Cu or a composition of Cu and Fe.

Abstract: An information handling system includes a first device having a first data communication interface connected to a first socket area of a socket. A second device includes a second data communication interface connected to a second socket area of the socket. A host processor includes a third data communication interface connected to a third socket area of the socket. When an interposer is installed into the socket in a first orientation, the interposer connects the first data communication interface to the third data communication interface. When the interposer is installed into the socket in a second orientation, the interposer connects the first data communication interface to the second data communication interface.

Abstract: An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.

Abstract: An inverting apparatus comprises: a DC port; an AC port; five switches; a first capacitor coupled between the first terminal of the second switch and the second terminal of the fourth switch; and a free-wheeling element coupled between the second terminal of the third switch and the second terminal of the fifth switch; wherein the five switches are controlled so that the device can switch among a plurality of operating modes and transmit active or reactive power to a power grid.